adv7189b Analog Devices, Inc., adv7189b Datasheet
adv7189b
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adv7189b Summary of contents
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... The output control signals allow glueless interface connections in almost any application. The ADV7189B modes are set up over a 2-wire, serial, bidirectional port (I The ADV7189B is fabricated in a 3.3 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. The ADV7189B is packaged in a small, 80-lead LQFP Pb-free package ...
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... ADV7189B TABLE OF CONTENTS Introduction ...................................................................................... 4 Analog Front End ......................................................................... 4 Standard Definition Processor ................................................... 4 Functional Block Diagram .............................................................. 5 Specifications..................................................................................... 6 Electrical Characteristics............................................................. 6 Video Specifications..................................................................... 7 Timing Specifications .................................................................. 8 Analog Specifications................................................................... 8 Thermal Specifications ................................................................ 9 Timing Diagrams.......................................................................... 9 Absolute Maximum Ratings.......................................................... 10 ESD Caution................................................................................ 10 Pin Configuration and Function Descriptions........................... 11 Analog Front End ........................................................................... 13 Analog Input Muxing ................................................................ 13 Global Control Registers ...
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... Changes to Table 86 ........................................................................91 Changes to Table 87 ........................................................................92 Changes to Table 88 ........................................................................93 Changes to Table 89 ........................................................................94 Added XTAL Load Capacitor Value Section...............................99 Inserted Figure 44; Renumbered Sequentially ............................99 Changes to Figure 46 ....................................................................101 Updated Outline Dimensions......................................................102 Changes to Ordering Guide.........................................................102 Rev Page 3 of 104 ADV7189B ...
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... ADV7189B. The ADCs are configured to run in 4× oversampling mode. STANDARD DEFINITION PROCESSOR The ADV7189B is capable of decoding a large selection of base- band video signals in composite, S-Video, and component formats. The video standards supported by the ADV7189B include PAL B/D/I/G/H, PAL60, PAL M, PAL N, PAL Nc, NTSC M/J, NTSC 4 ...
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... FUNCTIONAL BLOCK DIAGRAM OUTPUT FORMATTER Figure 1. Rev Page 5 of 104 ADV7189B ...
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... Digital I/O Supply Current PLL Supply Current Analog Supply Current Power-Down Current Power-Up Time 1 Temperature range –40°C to +85°C. (0°C to 70°C for ADV7189BKSTZ) MIN MAX 2 The min/max specifications are guaranteed over this range. 3 Pin 36 and Pin 79. 4 Pin 1, Pin 2, Pin 5 to Pin 8, Pin 12, Pin 17 to Pin 24, Pin 32 to Pin 35, Pin 73 to Pin 76, and Pin 80. ...
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... Chroma Phase Error Chroma Luma Intermodulation LUMA SPECIFICATIONS Luma Brightness Accuracy Luma Contrast Accuracy 1 Temperature range –40°C to +85°C. (0°C to 70°C for ADV7189BKSTZ). MIN MAX 2 The min/max specifications are guaranteed over this range VDD ...
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... Large Clamp Source Current Large Clamp Sink Current Fine Clamp Source Current Fine Clamp Sink Current 1 Temperature range –40°C to +85°C. (0°C to 70°C for ADV7189BKSTZ). MIN MAX 2 The min/max specifications are guaranteed over this range VDD ...
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... Parameter THERMAL CHARACTERISTICS Junction-to-Case Thermal Resistance Junction-to-Ambient Thermal Resistance (Still Air) 1 Temperature range –40°C to +85°C. (0°C to 70°C for ADV7189BKSTZ) MIN MAX 2 The min/max specifications are guaranteed over this range. TIMING DIAGRAMS t 3 SDA SCLK OUTPUTS P0– ...
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... ADV7189B ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating A to GND 4 V VDD A to AGND 4 V VDD D to DGND 2.2 V VDD P to AGND 2.2 V VDD D to DGND 4 V VDDIO D to AVDD –0 +0.3 V VDDIO –0 +0.3 V VDD VDD D – P –0 VDDIO VDD D – ...
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... Figure 5. 80-Lead LQFP Pin Configuration Rev Page 11 of 104 AIN5 60 AIN11 59 AIN4 58 AIN10 57 AGND 56 CAPC2 55 CAPC1 54 AGND 53 CML 52 REFOUT 51 AVDD 50 CAPY2 49 CAPY1 48 AGND 47 AIN3 46 AIN9 45 AIN2 44 AIN8 43 AIN1 42 AIN7 ADV7189B ...
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... H modes for the ADV7189B. When set to a logic low, OE enables the pixel output bus, P19 toP0 of the ADV7189B. A logic high on the OE pin places Pins P19 to P0, HS, VS, SFL into a high impedance state. The recommended external loop filter must be connected to this ELPF pin, as shown in F igure 46 ...
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... ANALOG FRONT END ANALOG INPUT MUXING The ADV7189B has an integrated analog muxing section that allows more than one source of video signal to be connected to the decoder. F igure 6 outlines the overall structure of the input muxing provided in the ADV7189B. As can be seen in F igure 6, there are two different ways in which ...
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... ADI-recommended input muxing is designed to minimize YPrPb crosstalk between signal channels and to obtain the highest YPrPb level of signal integrity. YPrPb out should connect analog video signals to the ADV7189B. YPrPb It is strongly recommended to connect any unused analog input YPrPb pins to AGND to act as a shield. Composite ...
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... AIN12 1111 No Connection This means INSEL must be used to tell the ADV7189B whether the input signal is of component, YC, or CVBS format. Restrictions in the channel routing are imposed by the analog signal routing inside the IC; every input pin cannot be routed to each ADC. Refer to capabilities inside the chip ...
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... POWER-SAVE MODES Power-Down PDBP, Address 0x0F[2] The digital core of the ADV7189B can be shut down by using a pin ( PWRDN ) and a bit ( PWRDN , see below). The PDBP con- trols which of the two has the higher priority. The default is to give the pin ( PWRDN ) priority. This allows the user to have the ADV7189B powered down by default ...
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... When TOD is 1, the output drivers are three-stated. Three-State LLC Drivers TRI_LLC, Address 0x1D[7] This bit allows the output drivers for the LLC1 pin and LLC2 pin of the ADV7189B to be three-stated. For more information on three-state control, refer to the T hree-State Output Drivers and the T iming Signals Output Enable sections ...
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... SFL pin. Polarity LLC Pin PCLK Address 0x37[0] The polarity of the clock that leaves the ADV7189B via the LLC1 and LLC2 pins can be inverted using the PCLK bit. Changing the polarity of the LLC clock output can be necessary to meet the setup-and-hold time expectations of follow-on chips ...
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... An identification value of 0x13 indicates the ADV7189B silicon. STATUS 1 STATUS_1[7:0] Address 0x10[7:0] This read-only register provides information about the internal status of the ADV7189B. These bits are used to set VS free run (coast) frequency. See the V S_Coast[1:0], Address 0xF9[3:2]section and ...
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... F igure The ADV7189B block can handle standard definition video in CVBS, YC, and YPrPb formats. It can be divided into a lumi- nance and chrominance path. If the input video composite type (CVBS), both processing paths are fed with the CVBS input. ...
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... The raw sync information is sent to a line-length measurement and prediction block. The output of this is then used to drive the digital resampling section to ensure that the ADV7189B outputs 720 active pixels per line. The sync processing on the ADV7189B also includes the ...
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... ADV7189B AD_N443_EN Enable Autodetection of NTSC 443, Address 0x07[5] Setting AD_N443_EN to 0 disables the autodetection of NTSC style systems with a 4.43 MHz color subcarrier. Setting AD_N443_EN to 1 (default) enables the detection. AD_P60_EN Enable Autodetection of PAL60, Address 0x07[4] Setting AD_P60_EN to 0 disables the autodetection of PAL systems with field rate ...
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... Bits[1:0] in Status Register 1. This bit must be set to 0 when operating the ADV7189B in YPrPb component mode in order to generate a reliable HLOCK status bit. Setting FSCLE to 0 (default) makes the overall lock status dependent on only the horizontal sync lock ...
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... Cr channel 0xFF +312 mV offset applied to the Cr channel BRI[7:0] Brightness Adjust, Address 0x0A[7:0] This register controls the brightness of the video signal through the ADV7189B. It allows the user to adjust the brightness of the picture. Table 27. BRI Function BRI[7:0] Description 0x00 (default) ...
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... Because the input is ac-coupled into the decoder, its dc value needs to be restored. This process is referred to as clamping the video. This section explains the general process of clamping on the ADV7189B and shows the different ways in which a user can configure its behavior. The ADV7189B uses a combination of current sources and a ...
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... MHz. (In the case of 4× oversampled video, the ADCs sample at 54 MHz, and the first decimation is performed inside the DPP filters. Therefore, the data rate into the ADV7189B is always 27 MHz.) The ITU-R BT.601 recommends a sampling frequency of 13.5 MHz. The luma antialias filter decimates the oversampled video ...
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... An automatic mode for Y-shaped filtering is provided. In this mode, the ADV7189B evaluates the quality of the incoming video signal and selects the filter responses in accordance with the signal quality and video standard. YFSM, WYSFMOVR, and WYSFM allow the user to manually override these automatic decisions in part or in full. ...
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... ADV7189B Table 30. YSFM Function YSFM[4:0] Description 0'0000 Automatic selection including a wide-notch response (PAL/NTSC/SECAM) 0'0001 Automatic selection including a narrow-notch (default) response (PAL/NTSC/SECAM) 0'0010 SVHS 1 0'0011 SVHS 2 0'0100 SVHS 3 0'0101 SVHS 4 0'0110 SVHS 5 0'0111 SVHS 6 0'1000 SVHS 7 0'1001 SVHS 8 0'1010 SVHS 9 0'1011 SVHS 10 ...
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... Note: the data format at this point is CVBS for CVBS inputs, or chroma only for Y/C or Cr/Cb interleaved for YCrCb input formats. Chroma Antialias Filter (CAA). The ADV7189B over- x samples the CVBS by a factor of 2 and the Chroma/ factor decimating filter (CAA) is used to preserve the active video band and to remove any out-of- band components ...
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... VOLTAGE MINIMUM VOLTAGE GAIN OPERATION The gain control within the ADV7189B is done on a purely digital basis. The input ADCs support a 12-bit range, mapped into a 1.6 V analog voltage range. Gain correction takes place after the digitization in the form of a digital multiplier. Advantages of this architecture over the commonly used ...
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... Luma automatic gain value (LAGC[2:0] set to any of the x automatic modes) Table 36. LG/LMG Function LG[11:0]/LMG[11:0] Read/Write LMG[11: Write LG[11:0] Read Luma Gain Rev Page 31 of 104 ADV7189B Description Manual gain for luma path Actually used gain 4095 d 0 ... 2 (1) 2048 ...
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... Enable Manual Fixed Gain Mode: Set LAGC[2:0] to 000 BETACAM Enable Betacam Levels, Address 0x01[5] If YPrPb data is routed through the ADV7189B, the automatic gain control modes can target different video input levels, as outlined in. Note the BETACAM bit is valid only if the input mode is YPrPb (component). The BETACAM bit sets the target value for AGC operation ...
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... The threshold applies to only QAM- based (NTSC and PAL) or FM-modulated (SECAM) video standards. To enable the color kill function, the CKE bit must be set. For settings 000, 001, 010, and 011, chroma demodulation inside the ADV7189B may not work satisfactorily for poor input video signals. 0 ... 4 (2) Table 42 ...
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... ADV7189B CHROMA TRANSIENT IMPROVEMENT (CTI) The signal bandwidth allocated for chroma is typically much smaller than that of luminance. In the past, this was a valid way to fit a color video signal into a given overall bandwidth because the human eye is less sensitive to chrominance than to luminance. The uneven bandwidth, however, can lead to visual artifacts in sharp color transitions ...
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... The default value for DNR_TH[7:0] is 0x08, indicating the threshold for maximum luma edges to be interpreted as noise. COMB FILTERS The comb filters of the ADV7189B have been greatly improved to automatically handle video of all types, standards, and levels of quality. The NTSC and PAL configuration registers allow the ...
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... ADV7189B CCMN[2:0] Chroma Comb Mode NTSC, Address 0x38[5:3] Table 46. CCMN Function CCMN[2:0] Description 0xx (default) Adaptive comb mode. 100 Disable chroma comb. 101 Fixed chroma comb (top lines of line memory). 110 Fixed chroma comb (all lines of line memory). 111 Fixed chroma comb (bottom lines of line memory). ...
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... Fixed 4-line chroma comb for CTAPSP = 11. Configuration Adaptive 5 lines (3 taps) luma comb. Use low-pass/notch filter, see the Fixed 3 lines (2 taps) luma comb. Fixed 5 lines (3 taps) luma comb. Fixed 3 lines (2 taps) luma comb. Rev Page 37 of 104 ADV7189B Y -Shaping Filter section ...
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... All data for Line 1 to Line 21 is passed through and available at the output port. The ADV7189B does not blank the luma data, and automatically switches all filters along the luma data path into their widest bandwidth. For active video, the filter settings for YSH and YPK are restored ...
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... CTA[2:0] to have the chroma and luma data match delays for all modes of operation. If set, manual registers LTA[1:0] and CTA[2:0] are not used by the ADV7189B. If the automatic mode is disabled (via setting the AUTO_PDC_EN bit to 0), the values programmed into the LTA[1:0] and CTA[2:0] registers become active ...
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... ADV7189B SYNCHRONIZATION OUTPUT SIGNALS HS Configuration The following controls allow the user to configure the behavior of the HS output pin only: x Beginning of HS signal via HSB[10:0] End of HS signal via HSE[10:0] x Polarity of HS using PHS x The HS Begin and HS End registers allow the user to freely position the HS output (pin) within the video line ...
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... When PVS is 0 (default active high. When PVS active low. PF Polarity FIELD, Address 0x37[3] The polarity of the FIELD pin can be inverted using the PF bit. When (default), FIELD is active high. When FIELD is active low. Rev Page 41 of 104 ADV7189B ...
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... ADV7189B 525 OUTPUT VIDEO H V NVBEG[4:0] = 0x5 F NFTOG[4:0] = 0x3 262 263 264 265 OUTPUT VIDEO H V NVBEG[4:0] = 0x5 F NFTOG[4:0] = 0x3 1 APPLIES IF NEMAVMODE = 0: MUST BE MANUALLY SHIFTED IF NEWAVMODE = 1. Figure 21. NTSC Default (BT.656). The polarity and F is embedded in the data. 525 ...
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... The default value of NVBEG is 00101, indicating the NTSC 0 1 Vsync begin position. ADVANCE BY 0.5 LINE For all NTSC/PAL Vsync timing controls, both the V bit in the AV code and the Vsync on the VS pin are modified. Rev Page 43 of 104 ADV7189B Write 0x1A 0x81 0x84 0x00 0x00 0x7D 0xA1 ...
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... ADV7189B 1 NVENDSIGN ADVANCE END OF VSYNC BY NVEND[4:0] NOT VALID FOR USER PROGRAMMING ODD FIELD? YES NVENDDELO 1 0 ADDITIONAL DELAY BY 1 LINE VSEHO 1 0 ADVANCE BY 0.5 LINE VSYNC END Figure 24. NTSC Vsync End NVENDDELO NTSC Vsync End Delay on Odd Field, Address 0xE6[7] When NVENDDELO is 0 (default), there is no delay. ...
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... Hsync Position. Control 3 Polarity PAL_V_Bit_Beg PAL_V_Bit_End PAL_F_Bit_Tog FIELD FIELD 2 314 315 316 317 318 319 Rev Page 45 of 104 ADV7189B Write 0x1A 0x81 0x84 0x00 0x00 0x7D 0x29 0x41 0x84 0x06 PVEND[4:0] = 0x4 320 321 ...
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... ADV7189B 622 623 624 625 OUTPUT VIDEO HS OUTPUT VS OUTPUT FIELD OUTPUT 310 311 312 313 OUTPUT VIDEO HS OUTPUT VS OUTPUT FIELD OUTPUT Figure 27. PAL Typical Vsync/Field Positions Using Register Writes in 1 PVBEGSIGN ADVANCE BEGIN OF VSYNC BY PVBEG[4:0] NOT VALID FOR USER PROGRAMMING ODD FIELD? ...
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... Field signal on the FIELD/DE pin are modified. NOT VALID FOR USER Rev Page 47 of 104 1 PFTOGSIGN ADVANCE TOGGLE OF DELAY TOGGLE OF FIELD BY PTOG[4:0] FIELD BY PFTOG[4:0] PROGRAMMING ODD FIELD? YES PFTOGDELO PFTOGDELE ADDITIONAL ADDITIONAL DELAY BY 1 LINE FIELD TOGGLE Figure 30. PAL F Toggle ADV7189B DELAY BY 1 LINE ...
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... ADV7189B SYNC PROCESSING The ADV7189B has two additional sync processing blocks that postprocess the raw synchronization information extracted from the digitized input video. If desired, the blocks can be disabled via 2 the following two I C bits. ENHSPLL Enable Hsync Processor, Address 0x01[6] The Hsync processor is designed to filter incoming Hsyncs that have been corrupted by noise, providing improved performance for video signals with stable time bases but poor SNR ...
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... Rev Page 49 of 104 WSS2[5: ACTIVE VIDEO Register Default Value 0x91 Readback Only 0x92 Readback Only EDTV3[5:0] NOT SUPPORTED Register Default Value 0x93 Readback Only 0x94 Readback Only 0x95 Readback Only ADV7189B ...
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... ADV7189B CGMS Data Registers CGMS1[7:0], Address 0x96[7:0], CGMS2[7:0], Address 0x97[7:0], CGMS3[7:0], Address 0x98[7:0] F igure 33 shows the bit correspondence between the analog video waveform and the CGMS1/CGMS2/CGMS3 registers. CGMS3[7:4] are undetermined and should be masked out by software. +100 IRE +70 IRE 0 IRE – ...
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... Its end is programmable via LB_EL[3:0]. Detection at the Midrange Some transmissions of wide screen video include subtitles within the lower black box. If the ADV7189B finds at least two black lines followed by more nonblack video, for example, the subtitle, and is then followed by the remainder of the bottom black block, it reports back a midcount via LB_LCM[7:0] ...
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... ITU-R BT.1364). Checksum byte able 64 lists the values within a generic data packet that output by the ADV7189B in 10-bit format. SECONDARY DATA IDENTIFICATION DATA DID SDID USER DATA COUNT USER DATA ( WORDS) Figure 35 ...
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... T able 75 Gemstar 1× Format Half-byte output mode is selected by setting CDECAD = 0, full-byte output mode is selected by setting CDECAD = 1. See the G DECAD Gemstar Decode Ancillary Data Format Address 0x4C[0] section. Rev Page 53 of 104 ADV7189B Padding Bytes DC[1: ...
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... ADV7189B Table 66. Gemstar 2× Data, Half-Byte Mode Byte D[9] D[ !CS[8] CS[8] CS[7] Table 67. Gemstar 2× Data, Full-Byte Mode ...
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... User data-words 0 0 User data-words 0 0 User data-words CS[2] CS[1] CS[0] Checksum D[2] D[1] D[0] Description Fixed preamble Fixed preamble Fixed preamble DID 0 0 SDID Data count User data-words 0 0 User data-words UDW padding 0x200 UDW padding 0x200 CS[2] CS[1] CS[0] Checksum ADV7189B ...
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... ADV7189B NTSC CCAP Data Half-byte output mode is selected by setting CDECAD = 0; the full-byte mode is enabled by CDECAD = 1. See the Gemstar Decode Ancillary Data Format, Address 0x4C[0] section. The data packet formats are shown in T able 70 and T able 71 NTSC closed-caption data is sliced on line 21d on even and odd fields ...
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... T able 74 and Rev Page 57 of 104 ADV7189B Line Number (ITU-R BT.470) Enable Bit Comment 10 GDECOL[0] Gemstar 11 GDECOL[1] Gemstar 12 GDECOL[2] Gemstar 13 GDECOL[3] Gemstar 14 GDECOL[4] Gemstar 15 GDECOL[5] Gemstar 16 GDECOL[6] Gemstar ...
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... H Not valid Interrupt System P P Not valid The ADV7189B has a comprehensive interrupt register set. This Not valid map is located in the Register Access. See Closed caption the interrupt register map. How to access this map is described Not valid in F igure 38. ...
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... INTRQ_OP_SEL[1:0] for a logic level to be driven out from the INTRQ pin also possible to write to a register in the ADV7189B that manually asserts the INTRQ pin. This bit is MPU_STIM_INTRQ. INTRQ_OP_SEL[1:0], Interrupt Duration Select Address 0x40 (Interrupt Space)[1:0] Table 77 ...
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... ADV7189B PIXEL PORT CONFIGURATION The ADV7189B has a very flexible pixel port that can be config- ured in a variety of formats to accommodate downstream ICs. T able 79 and T able 80 summarize the various functions that the ADV7189B pins can have in different modes of operation. ...
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... C master reads information from the peripheral. The ADV7189B acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit. The ADV7189B has 249 subaddresses to enable access to the internal registers able 81 ...
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... ADV7189B REGISTER ACCESSES The MPU can write to or read from most of the ADV7189B’s registers, excepting the registers that are read-only or write- only. The subaddress register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the subaddress register ...
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... Rev Page 63 of 104 ADV7189B Subaddress Dec Hex 0 0x00 1 0x01 2 0x02 3 0x03 4 0x04 5 0x05 6 0x06 7 0x07 8 0x08 9 0x09 10 ...
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... ADV7189B Register Name Reserved Resample Control Reserved Gemstar Ctrl 1 Gemstar Ctrl 2 Gemstar Ctrl 3 Gemstar Ctrl 4 GemStar Ctrl 5 CTI DNR Ctrl 1 CTI DNR Ctrl 2 Reserved CTI DNR Ctrl 4 Lock Count Reserved Free Run Line Length 1 Reserved VBI Info WSS 1 WSS 2 EDTV 1 EDTV 2 ...
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... NSFSEL.1 VS_JIT_COMP_EN CTA.2 CTA.1 CTA.0 LAGC.1 LAGC.0 CMG.11 CMG.5 CMG.4 CMG.3 LMG.11 LMG.5 LMG.4 LMG.3 NEWAVMODE HVSTIM Rev Page 65 of 104 ADV7189B Subaddress Dec Hex 244 0xF4 245 to 247 0xF5 to 0xF7 248 0xF8 249 0xF9 Bit 2 Bit 1 Bit 0 INSEL.2 INSEL.1 INSEL.0 OF_SEL ...
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... ADV7189B Register Name Bit 7 Bit 6 Vsync Field VSBHO VSBHE Control 2 Vsync Field VSEHO VSEHE Control 3 Hsync Position HSB.10 Control 1 Hsync Position HSB.7 HSB.6 Control 2 Hsync Position HSE.7 HSE.6 Control 3 Polarity PHS NTSC Comb CTAPSN.1 CTAPSN.0 Control PAL Comb CTAPSP.1 CTAPSP.0 Control ...
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... Q_MSKB SCM_LOCK PAL_SW_LK SCM_LOCK _CHNG_Q _CHNG_Q PAL_SW_L SCM_LOCK K_CHNG_ _CHNG_ CLR CLR PAL_SW_ SCM_LOCK LK_CHNG_ _CHNG_ MSKB MSKB Rev Page 67 of 104 ADV7189B Bit 2 Bit 1 Bit 0 SD_OFF_CB.2 SD_OFF_CB.1 SD_OFF_CB.0 SD_OFF_CR.2 SD_OFF_CR .1 SD_OFF_CR.0 SD_SAT_CB.2 SD_SAT_CB.1 SD_SAT_CB.0 SD_SAT_CR.2 SD_SAT_CR.1 SD_SAT_CR.0 NVBEG.2 NVBEG.1 NVBEG.0 NVEND ...
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... ADV7189B INTERRUPT REGISTER MAP The following registers are located in Register Access Page 2. Table 85. Interrupt (Page 2) Register Map Details Subaddress Register Bit Description 0x40 Interrupt INTRQ_OP_SEL[1:0]. Config 1 Interrupt Drive Level Select Register Access MPU_STIM_INTRQ[1:0]. Page 2 Manual Interrupt Set Mode Reserved MV_INTRQ_SEL[1:0]. ...
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... Do not clear 1 Clears CGMS_CHNGD_Q bit 0 Do not clear 1 Clears WSS_CHNGD_Q bit x Not used x Not used x Not used 0 Do not clear 1 Clears MPU_STIM_INTRQ_Q bit Rev Page 69 of 104 ADV7189B Notes These bits can be cleared or masked by Register 0x47 and Register 0x48, respectively. ...
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... ADV7189B Subaddress Register Bit Description 0x48 Interrupt CCAPD_MSKB Mask 2 GEMD_MSKB Read/ Write CGMS_CHNGD_MSKB Register WSS_CHNGD_MSKB Access Page 2 Reserved Reserved Reserved MPU_STIM_INTRQ_MSKB 0x49 Raw Status SD_OP_50Hz 3 SD 60/50Hz frame rate at output Read Only SD_V_LOCK Register Register Access SD_H_LOCK Page 2 Reserved SCM_LOCK SECAM Lock ...
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... Unmasks SD_OP_CHNG_Q bit 0 Masks SD_V_LOCK_CHNG_Q bit 1 Unmasks SD_V_LOCK_CHNG_Q bit 0 Masks SD_H_LOCK_CHNG_Q bit 1 Unmasks SD_H_LOCK_CHNG_Q bit 0 Masks SD_AD_CHNG_Q bit 1 Unmasks SD_AD_CHNG_Q bit 0 Masks SCM_LOCK_CHNG_Q bit 1 Unmasks SCM_LOCK_CHNG_Q bit 0 Masks PAL_SW_LK_CHNG_Q bit 1 Unmasks PAL_SW_LK_CHNG_Q bit x Not used x Not used Rev Page 71 of 104 ADV7189B Notes ...
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... ADV7189B The following registers are located in the Common I Table 86. Common and Normal (Page 1) Register Map Details Subaddress Register Bit Description 0x00 Input INSEL[3:0]. The INSEL bits allow the Control user to select an input channel as well as the input format. VID_SEL[3:0]. The VID_SEL bits allow the user to select the input video standard ...
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... HS, VS, F three-stated 1 HS, VS, F forced active BT656-3-compatible 1 BT656-4-compatible Rev Page 73 of 104 ADV7189B Notes See also TIM_OE and TRI_LLC ITU-R BT.656 Extended range SFL output enables encoder and decoder to be connected directly. During VBI Controlled by TOD ...
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... ADV7189B Subaddress Register Bit Description 0x07 Autodetect AD_PAL_EN. PAL B/G/I/H Enable autodetect enable. AD_NTSC_EN. NTSC autodetect enable. AD_PALM_EN. PAL M autodetect enable. AD_PALN_EN. PAL N autodetect enable. AD_P60_EN. PAL 60 autodetect enable. AD_N443_EN. NTSC443 autodetect enable. AD_SECAM_EN. SECAM autodetect enable. AD_SEC525_EN. SECAM 525 autodetect enable. ...
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... Detected standard. NTSC-443 PAL-M PAL-60 PAL-BGHID SECAM PAL combination N SECAM 525 Color kill is active = 1 Color kill. x ADV7189B = 0x13 x MV color striping detected 1 = Detected MV color striping type 0 = Type Type 3 MV pseudo sync detected 1 = Detected MV AGC pulses detected 1 = Detected Nonstandard line length ...
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... ADV7189B Subaddress Register Bit Description 0x15 Digital Reserved Clamp DCT[1:0]. Digital clamp timing Control 1 determines the time constant of the digital fine clamp circuitry. Reserved 0x17 Shaping YSFM[4:0]. Selects Y-Shaping Filter Filter mode when in CVBS only mode. Control Allows the user to select a wide range of low-pass and notch filters ...
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... Medium 1 0 Wide 1 1 Widest 0 0 Narrow 0 1 Medium 1 0 Medium 1 1 Wide Set as default Set to default 0 Enabled 1 Disabled 0 Use 27 MHz crystal 1 Use 28 MHz crystal 0 LLC pin active 1 LLC pin three-stated Rev Page 77 of 104 ADV7189B Notes ...
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... ADV7189B Subaddress Register Bit Description 0x27 Pixel Delay LTA[1:0]. Luma timing adjust allows Control the user to specify a timing difference between chroma and luma samples. Reserved CTA[2:0]. Chroma timing adjust allows a specified timing difference between the luma and chroma samples AUTO_PDC_EN. Automatically ...
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... VS goes low in the middle of the line (odd field changes state at the start of the line (odd field) Rev Page 79 of 104 ADV7189B Notes CAGC[1:0] settings decide in which mode CMG[11:0] operates Has an effect only if CAGC[1:0] is set to auto gain (10) Min value is 0 dec (G = – ...
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... ADV7189B Subaddress Register Bit Description 0x34 HS Position HSE[10:8]. HS end allows the Control 1 positioning of the HS output within the video line. Reserved HSB[10:8]. HS begin allows the positioning of the HS output within the video line. Reserved 0x35 HS Position HSB[7:0] See above, using Control 2 HSB[10:0] and HSE[10:0], the user can program the position and length of HS output signal ...
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... Adapts 3 lines – 2 lines 0 1 Not used 1 0 Adapts 5 lines – 3 lines 1 1 Adapts 5 lines – 4 lines Rev Page 81 of 104 ADV7189B Notes Top lines of memory All lines of memory Bottom lines of memory Top lines of memory All lines of memory Bottom lines of ...
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... ADV7189B Subaddress Register Bit Description 0x39 PAL Comb YCMP[2:0]. luma comb mode, PAL. Control CCMP[2:0]. chroma comb mode, PAL. CTAPSP[1:0]. chroma comb taps, PAL. 0x3A Reserved PWRDN_ADC_2. Enables power- down of ADC2. PWRDN_ADC_1. Enables power- down of ADC1. PWRDN_ADC_0. Enables power- down of ADC0. ...
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... Set to 0x04 for A/V input; set to 0x0A for tuner input Rev Page 83 of 104 ADV7189B Notes LSB = Line 10 MSB = Line 25 Default = Do not check for Gemstar- compatible data on any lines (10 to 25) in even fields LSB = Line 10 MSB = Line 25 Default = Do not ...
Page 84
... ADV7189B Subaddress Register Bit Description 0x51 Lock Count CIL[2:0]. Count-into-lock determines the number of lines the system must remain in lock before showing a locked status. COL[2:0]. Count-out-of-lock determines the number of lines the system must remain out-of-lock before showing a lost-locked status. SRLS. Select raw lock signal. Selects the determination of the lock ...
Page 85
... AIN11 AIN12 connection Rev Page 85 of 104 ADV7189B Notes This feature examines the active video at the start and at the end of each field. It enables format detection even if the video is not accompanied by a CGMS or WSS sequence. SETADC_sw_man_ ...
Page 86
... ADV7189B Subaddress Register Bit Description 0xC4 ADC ADC2_SW[3:0]. Manual muxing SWITCH 2 control for ADC2. Reserved ADC_SW_MAN_EN. Enable manual setting of the input signal muxing. 0xDC Letterbox LB_TH[4:0]. Sets the threshold Control 1 value that determines if a line is black. Reserved 0xDE Reserved 0xDD Letterbox LB_EL[3:0] ...
Page 87
... Additional delay by 1 line 0 No delay 1 Additional delay by 1 line PAL default (BT.656) 0 Set to low when manual programming 1 Not suitable for user programming 0 No delay 1 Additional delay by 1 line 0 No delay 1 Additional delay by 1 line Rev Page 87 of 104 ADV7189B Notes ...
Page 88
... ADV7189B Subaddress Register Bit Description 0xE9 PAL V Bit PVEND[4:0]. How many lines after End l rollover to set V low. COUNT PVENDSIGN PVENDDELE. Delay V bit going low by one line relative to PVEND (even field). PVENDDELO. Delay V bit going low by one line relative to PVEND (odd field). ...
Page 89
... Limit minimum Vsync frequency to 42.75 Hz (731 lines/frame) 1 Limit minimum Vsync frequency to 39.51 Hz (791 lines/frame Auto Coast mode Coast mode Coast mode 1 1 Reserved Rev Page 89 of 104 ADV7189B Notes This value sets up the output coast frequency. ...
Page 90
... ADV7189B PROGRAMMING EXAMPLES EXAMPLES USING 28 MHz CLOCK Mode 1 CVBS Input (Composite Video on AIN5) All standards are supported through autodetect, 10-bit, 4:2:2, ITU-R BT.656 output on P19 to P10. Table 87. Mode 1 CVBS Input Register Address Register Value Notes 0x00 0x04 CVBS input on AIN5. 0x03 0x00 Enable 10-bit output on P19 to P10 ...
Page 91
... Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Rev Page 91 of 104 ADV7189B ...
Page 92
... ADV7189B Mode 3 YPrPb Input 525i/625i (Y on AIN2 AIN3, and Pb on AIN6) All standards are supported through autodetect, 10-bit, ITU-R BT.656 output on P19 to P10. Table 89. Mode 3 YPrPb Input 525i/625i Register Address Register Value 0x00 0x0A 0x03 0x00 0x1D 0x40 0x0F 0x40 ...
Page 93
... Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Rev Page 93 of 104 ADV7189B ...
Page 94
... ADV7189B EXAMPLES USING 27 MHz CLOCK Mode 1 CVBS Input (Composite Video on AIN5) All standards are supported through autodetect, 10-bit, 4:2:2, ITU-R BT.656 output on P19 to P10. Table 91. Mode 1 CVBS Input Register Address Register Value 0x00 0x04 0x03 0x00 0x15 0x00 0x17 0x41 0x3A 0x16 ...
Page 95
... Set DNR threshold to 4 for flat response. ADI recommended programming sequence. This sequence must be followed exactly when setting up the decoder. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Rev Page 95 of 104 ADV7189B ...
Page 96
... ADV7189B Mode 4 CVBS Tuner Input PAL Only on AIN4 10-bit, ITU-R BT.656 output on P19 to P10. Table 94. Mode 4 CVBS Tuner Input PAL Only Register Address Register Value 0x00 0x83 0x03 0x00 0x07 0x01 0x15 0x00 0x17 0x41 0x19 0xFA 0x3A 0x16 0x50 0x0A ...
Page 97
... EMI, and reduce the current spikes inside the ADV7189B. If series resistors are used, place them as close as possible to the ADV7189B pins. However, try not to add vias or extra length to the output trace to make the resistors closer. If possible, limit the capacitance that each of the digital outputs drives to less than 15 pF ...
Page 98
... CRYSTAL LOAD CAPACITOR VALUE SELECTION F igure 44 shows an example reference clock circuit for the ADV7189B. Special care must be taken when using a crystal cir- cuit to generate the reference clock for the ADV7189B. Small variations in reference clock frequency can cause autodetection issues and impair the ADV7189B performance. ...
Page 99
... TYPICAL CIRCUIT CONNECTION Examples of how to connect the ADV7189B video decoder are shown in the ADV7189B, refer to the ADV7189B evaluation note. IN Figure 45. ADI Recommended Anti-Aliasing Circuit for All Input Channels F igure 45 and AVDD_5V R43 BUFFER 0: R39 C93 C 4.7k: 100PF B FILTER Q6 R53 L10 ...
Page 100
... FERRITE BEAD AVDD (3.3V) 33PF 10PF AGND AGND FERRITE BEAD DVDD (1.8V) 33PF 10PF DGND DGND 100nF AIN1 AIN7 100nF AIN2 AIN8 100nF AIN3 ADV7189B AIN9 100nF AIN4 AIN10 100nF AIN5 AIN11 100nF AIN6 AIN12 AGND AGND CAPY1 + 10PF 0.1PF 1nF CAPY2 CAPC1 + 10PF ...
Page 101
... The ADV7189B is a Pb-free, environmentally friendly product manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications, and can withstand surface-mount soldering 255°C (±5°C). In addition backward-compatible with conventional SnPb soldering processes. This means the electroplated Sn coating can be soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220° ...
Page 102
... ADV7189B NOTES Rev Page 102 of 104 ...
Page 103
... NOTES Rev Page 103 of 104 ADV7189B ...
Page 104
... ADV7189B NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...