lm8328tmx National Semiconductor Corporation, lm8328tmx Datasheet
lm8328tmx
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... LM8328 Function Blocks © 2011 National Semiconductor Corporation LM8328 Any pin programmed as an input can also sense hardware interrupts. The interrupt polarity (“high to low” or “low to high” ...
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Features 4.1 KEY FEATURES • Internal RC oscillator, no external clock required • Internal PWM clock generation, no external clock required • External reset for system control • Programmable I 2 C-compatible ACCESS.bus address (Default 0x88) • Support for ...
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General Description ......................................................................................................................... 1 2.0 Applications: ................................................................................................................................... 1 3.0 LM8328 Function Blocks .................................................................................................................. 1 4.0 Features ........................................................................................................................................ 2 4.1 KEY FEATURES ...................................................................................................................... 2 4.2 HOST-CONTROLLED FEATURES ............................................................................................. 2 4.3 KEY DEVICE FEATURES ......................................................................................................... 2 5.0 Pin Assignments ............................................................................................................................. 2 ...
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TIMIC - PWM Timer Interrupt Clear Register .................................................................. 26 13.2.7 PWMWP - PWM Timer Pattern Pointer Register ............................................................. 27 13.2.8 PWMCFG - PWM Script Register .................................................................................. 27 13.3 INTERFACE CONTROL REGISTERS ..................................................................................... 28 13.3.1 I2CSA - I 2 C-Compatible ...
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PWM Timer Registers ................................................................................................. 49 16.1.3 System Registers ....................................................................................................... 50 16.1.4 Global Interrupt Registers ............................................................................................ 50 16.1.5 GPIO Registers .......................................................................................................... 50 17.0 Physical Dimensions .................................................................................................................... 57 5 www.national.com ...
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... Ordering Information NSID LM8328TME LM8328TMX 7.0 Signal Descriptions 7.1 DEVICE PIN FUNCTIONS TABLE 1. KEY AND ALTERNATE FUNCTIONS OF ALL DEVICE PINS Ball Function 0 C1 Reset Active Low Input C4 Supply Voltage D1 Main Clk E1 Main Data A5 Keypad-I Keypad-I Keypad-I Keypad-I ...
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TABLE 2. Pin Configuration after Reset Pins KPX0 KPX1 KPX2 KPX3 Full Buffer mode with an on-chip pull up resistor enabled. KPX4 KPX5 KPX6 KPX7 KPY0 KPY1 KPY2 KPY3 KPY4 KPY5 Full Buffer mode with an on-chip pull down resistor ...
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Typical Application Setup FIGURE 3. LM8328 in a Typical Setup with Standard Handset Keypad 8.1 FEATURES The following features are supported with the application example shown in example above: 8.1.1 Hardware Hardware • keys and 8 ...
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Halt Mode 9.1 HALT MODE DESCRIPTION The fully static architecture of the LM8328 allows stopping the internal RC clock in Halt mode, which reduces power con- sumption to the minimum level. Figure 4 Halt mode at the maximum VCC ...
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LM8328 Programming Interface The LM8328 operation is controlled from a host device by a complete register set, accessed via the I ACCESS.bus interface. The ACCESS.bus communication is based on a READ/WRITE structure, following the I FIGURE 5. Master/Slave Serial ...
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Communication Initialized from Host (Restart from Sleep Mode) FIGURE 6. Host Starts Communication While LM8328 is in Sleep Mode • In the timing diagram shown in Figure 6 slave address the host must generate a STOP condition followed by ...
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Step Master/Slave Step Master/Slave ADDR ...
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Keyscan Operation 11.1 KEYSCAN INITIALIZATION 11.2 KEYSCAN INITIALIZATION EXAMPLE Table 6 shows all the LM8328 register configurations to ini- tialize keyscan: Access Register name adress CLKEN 0x8A KBDSETTLE 0x01 KBDBOUNCE 0x02 KBDSIZE 0x03 KBDDEDCFG 0x04 IOCFG 0xA7 IOPC0 0xAA ...
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KEYSCAN PROCESS The LM8328 keyscan functionality is based on a specific scanning procedure performed in a 4ms interval. On each scan all assigned key matrix pins are evaluated for state changes. In case a key event has been identified, ...
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FIGURE 9. Example Host Reacting to Interrupt for Keypad Event 15 30124109 www.national.com ...
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MULTIPLE KEY PRESSES The LM8328 supports up to four simultaneous key presses. Any time a single key is pressed KBDCODE0 is set with the appropriate key code second key is pressed, the key is stored in KBDCODE1 ...
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RAMP COMMAND A RAMP command will vary the duty cycle of a PWM output in either direction (up or down). The INCREMENT field spec- ifies the amount of steps for the RAMP. The maximum amount of steps which can ...
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TABLE 14. Description of Bit and Building Fields of the BRANCH Command Bit or Field Value 0 LOOPCOUNT ADDR 1 STEPNUMBER 12.2.5 TRIGGER COMMAND Triggers are used to synchronize operations between PWM channels. ...
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LM8328 Register Set 13.1 KEYBOARD REGISTERS AND KEYBOARD CONTROL Keyboard selection and control registers are mapped in the address range from 0x01 to 0x10. This paragraph describes the functions of the associated registers down to the bit level. 13.1.1 ...
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KBDDEDCFG - Dedicated Key Register Register - Name Address KBDDEDCFG 0x04 Bit - Name Bit ROW[7:2] 15:10 COL[11:10] 9:8 COL[9:2] 7:0 13.1.5 KBDRIS - Keyboard Raw Interrupt Status Register TABLE 23. KBDRIS - Keyboard Raw Interrupt Status Register Register ...
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KBDMIS - Keypad Masked Interrupt Status Register TABLE 24. KBDMIS - Keypad Masked Interrupt Status Register Register - Name Address KBDMIS 0x07 Bit - Name Bit (reserved) 7:4 MELINT 3 MEVTINT 2 MKLINT 1 MSINT 0 13.1.7 KBDIC - ...
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Register - Name Address (reserved) 7:4 MSKELINT 3 MSKEINT 2 MSKLINT 1 MSKSINT 0 13.1.9 KBDCODE0 - Keyboard Code Register 0 The key code detected by the keyboard scan can be read from the registers KBDCODE0: KBDCODE3 ...
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KBDCODE3 - Keyboard Code Register 3 TABLE 30. KBDCODE3 - Keyboard Code Register 3 Register - Name Address KBDCODE3 0x0E Bit - Name Bit MULTIKEY 7 KEYROW[2:0] 6:4 KEYCOL[3:0] 3:0 13.1.13 EVTCODE - Key Event Code Register TABLE 31. ...
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PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Registers TABLE 33. PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Registers Register - Name Address PWMCFG0 0x61 PWMCFG1 0x69 PWMCFG2 0x71 Bit - Name Bit (x ...
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TIMRIS - PWM Timer Interrupt Status Register TABLE 35. TIMRIS - PWM Timer Interrupt Status Register Register - Name Address TIMRIS 0x7A Bit - Name Bit (reserved) 7:6 CDIRQ2 5 CDIRQ1 4 CDIRQ0 3 CYCIRQ2 2 CYCIRQ1 1 CYCIRQ0 ...
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Register - Name Address CDIRQ2 5 CDIRQ1 4 CDIRQ0 3 CYCIRQ2 2 CYCIRQ1 1 CYCIRQ0 0 13.2.6 TIMIC - PWM Timer Interrupt Clear Register TABLE 37. TIMIC - PWM Timer Interrupt Clear Register Register - Name Address TIMIC 0x7C Bit ...
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Register - Name Address CYCIRQ0 0 13.2.7 PWMWP - PWM Timer Pattern Pointer Register TABLE 38. PWMWP - PWM Timer Pattern Pointer Register Register - Name Address PWMWP 0x7D Bit - Name Bit (reserved) 7 POINTER[6:0] 6:0 13.2.8 PWMCFG - ...
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INTERFACE CONTROL REGISTERS The following section describes the functions of special con- trol registers provided for the main controller. The manufacturer code MFGCODE and the software revision number SWREV tell the main device which configuration file has to be ...
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Register - Name Address RSTCTRL 0x82 Bit - Name Bit (reserved) 7:5 IRQRST 4 TIMRST 3 (reserved) 2 KBDRST 1 GPIRST 0 13.3.6 RSTINTCLR - Clear NO Init/Power-On Interrupt Register TABLE 45. RSTINTCLR - Clear NO Init/Power-On Interrupt Register Register ...
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CLKEN - Clock Enable Register Register - Name Address CLKEN 0x8A Bit - Name Bit (reserved) 7:3 TIMEN 2 (reserved) 1 KBDEN 0 13.3.9 AUTOSLIP - Autosleep Enable Register Register - Name Address AUTOSLP 0x8B Bit - Name Bit ...
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IRQST - Global Interrupt Status Register TABLE 50. IRQST - Global Interrupt Status Register Register - Name Address IRQST 0x91 Bit - Name Bit PORIRQ 7 KBDIRQ 6 (reserved) 5:4 TIM2IRQ 3 TIM1IRQ 2 TIM0IRQ 1 GPIOIRQ 0 Type ...
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GPIO FEATURE CONFIGURATION 13.4.1 GPIO Feature Mapping The LM8328 has a flexible IO structure which allows to dy- namically assign different functionality to each ball. The func- tionality of each ball is determined by the complete configu- ration of ...
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Register - Name Address KPX5PR[1:0] 11:10 KPX4PR[1:0] 9:8 KPX3PR[1:0] 7:6 KPX2PR[1:0] 5:4 KPX1PR[1:0] 3:2 KPX0PR[1:0] 1:0 * written values of 0x2 and 0x3 will always be read back as 0x3 13.4.4 IOPC1 - Pull Resistor Configuration Register 1 TABLE 54. ...
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Register - Name Address KPY2PR[1:0] 5:4 KPY1PR[1:0] 3:2 KPY0PR[1:0] 1:0 ** written values of 0x2 and 0x3 will always be read back as 0x3 13.4.5 IOPC2 - Pull Resistor Configuration Register 2 TABLE 55. IOPC2 - Pull Resistor Configuration Register ...
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GPIOOMS0 - GPIO Open Drain Mode Select Register 0 TABLE 57. GPIOOMS0 - GPIO Open Drain Mode Select Register 0 Register - Name Address GPIOOMS0 0xE1 Bit - Name Bit KPX[7:0]ODM 7:0 13.4.8 GPIOOME1 - GPIO Open Drain Mode ...
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GPIOOMS2 - GPIO Open Drain Mode Select Register 2 TABLE 61. GPIOOMS2 - GPIO Open Drain Mode Select Register 2 Register - Name Address GPIOOMS2 0xE5 Bit - Name Bit (reserved 7:4 KPY[11:8]ODM 3:0 13.5 GPIO DATA INPUT/OUTPUT 13.5.1 ...
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Register - Name Address MASK2 10 MASK1 9 MASK0 8 DATA7 7 DATA6 6 DATA5 5 DATA4 4 DATA3 3 DATA2 2 DATA1 1 DATA0 0 13.5.2 GPIOPDATA1 - GPIO Data Register 1 TABLE 63. GPIOPDATA1 - GPIO Data Register ...
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Register - Name Address MASK8 8 DATA15 7 DATA14 6 DATA13 5 DATA12 4 DATA11 3 DATA10 2 DATA9 1 DATA8 0 13.5.3 GPIOPDATA2 - GPIO Data Register 2 Register - Name Address GPIODATA2 0xC4 Bit - Name Bit (reserved) ...
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GPIOPDIR0 - GPIO Port Direction Register 0 TABLE 65. GPIOPDIR0 - GPIO Port Direction Register 0 Register - Name Address GPIODIR0 0xC6 Bit - Name Bit KPX[7:0]DIR 7:0 13.5.5 GPIOPDIR1 - GPIO Port Direction Register 1 TABLE 66. GPIOPDIR1 ...
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GPIOIS1 - Interrupt Sense Configuration Register 1 TABLE 69. GPIOIS1 - Interrupt Sense Configuration Register 1 Register - Name Address GPIOIS1 0xCA Bit - Name Bit KPY[7:0]IS 7:0 13.6.3 GPIOIS2 - Interrupt Sense Configuration Register 2 TABLE 70. GPIOIS2 ...
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GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2 TABLE 73. GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2 Register - Name Address GPIOIBE2 0xCE Bit - Name Bit (reserved 7:4 KPY[11:8]IBE 3:0 13.6.7 GPIOIEV0 - GPIO Interrupt Edge Select ...
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GPIOIE0 - GPIO Interrupt Enable Register 0 TABLE 77. GPIOIE0 - GPIO Interrupt Enable Register 0 Register - Name Address GPIOIE0 0xD2 Bit - Name Bit KPX[7:0]IE 7:0 13.6.11 GPIOIE1 - GPIO Interrupt Enable Register 1 TABLE 78. GPIOIE1 ...
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GPIOIC2 - GPIO Clear Interrupt Register 2 TABLE 82. GPIOIC2 - GPIO Clear Interrupt Register 2 Register - Name Address GPIOIC2 0xDE Bit - Name Bit (reserved) 7:4 KPY[11:8]IC 3:0 13.7 GPIO INTERRUPT STATUS 13.7.1 GPIORIS0 - Raw Interrupt ...
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GPIOMIS0 - Masked Interrupt Status Register 0 TABLE 86. GPIOMIS0 - Masked Interrupt Status Register 0 Register - Name Address GPIOMIS0 0xD9 Bit - Name Bit KPX[7:0]MIS 7:0 13.7.5 GPIOMIS1 - Masked Interrupt Status Register 1 TABLE 87. GPIOMIS1 ...
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GPIOWAKE1 - GPIO Wake-Up Register 1 TABLE 90. GPIOWAKE1 - GPIO Wake-Up Register 1 Register - Name Address GPIOWAKE1 0xEA Bit - Name Bit KPY[7:0]WAKE 7:00 13.8.3 GPIOWAKE2 - GPIO Wake-Up Register 2 TABLE 91. GPIOWAKE2 - GPIO Wake-Up ...
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Absolute Maximum Ratings 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Generic IOs Voltage at Backdrive/Overvoltage IOs 15.0 Electrical Characteristics Datasheet ...
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Parameter ACCESS.bus Output Signals SDA Hold Time (t ) (Note 4) SDAho Characteristics for all pins except IRQN/KPY11/PWM2, SDA, and SCL in GPIO mode. Parameter V (Min. Input High Voltage (Max. Input Low Voltage Source I ...
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Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test conditions, ...
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Registers 16.1 REGISTER MAPPING 16.1.1 Keyboard Registers Table 97 shows the register map for keyboard functionality. In addition to Global Call Reset (see Section 16.1.4 Global Interrupt Registers) or Software Reset using SWRESET (see TABLE 97. Register Map for ...
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Register Name Description PWM Timer TIMRIS Interrupt Status PWM Timer TIMMIS Masked Int. Status Timer Interrupt TIMIC Clear PWM Command PWMWP Write Pointer PWM Command PWMCFG Script 16.1.3 System Registers Table 99 shows the register map for general system registers. ...
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TABLE 101. Register Map for GPIO Functionality Register Name Description I/O Pin Mapping IOCFG Configuration Pull Resistor IOPC0 Configuration 0 Pull Resistor IOPC1 Configuration 1 Pull Resistor IOPC2 Configuration 2 GPIODATA0 GPIO I/O Data 0 GPIOMASK0 GPIO I/O Mask 0 ...
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Register Name Description GPIO Masked Int GPIOMIS0 Status 0 GPIO Masked Int GPIOMIS1 Status 1 GPIO Masked Int GPIOMIS2 Status 2 GPIO Interrupt GPIOIC0 Clear 0 GPIO Interrupt GPIOIC1 Clear 1 GPIO Interrupt GPIOIC2 Clear 2 GPIO Open Drain GPIOOME0 ...
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... Physical Dimensions Note: The bump numbering shown on the above package physical dimension is for reference only. Refer to Order Number LM8328TME NOPB or LM8328TMX NOPB inches (millimeters) unless otherwise noted Micro SMD Package X1 = 2015 µm ± 30 µ 2015 µm ± 30 µ 600 mm ± 75 µm ...
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