tsc21020f ATMEL Corporation, tsc21020f Datasheet - Page 8

• Manufacturer Part Number: tsc21020f
• Description: Rad. Hard 32/40-bit Ieee Floating Point Dsp
• Manufacturer: ATMEL Corporation

Instruction Cache
Context Switching
Interrupts
Timer
8
TSC21020F
the access. To implement automatic modulo addressing for circular buffers, the
TSC21020F provides buffer length registers that can be associated with each pointer.
Base values for pointers allow circular buffers to be placed at arbitrary locations. Each
DAG register has an alternate register that can be activated for fast context switching.
The program sequencer supplies instruction addresses to program memory. It controls
loop iterations and evaluates conditional instructions. To execute looped code with zero
overhead, the TSC21020F maintains an internal loop counter and loop stack. No explicit
jump or decrement instructions are required to maintain the loop.
The TSC21020F derives its high clock rate from pipelined fetch, decode and execute
cycles. Approximately 70% of the machine cycle is available for memory accesses; con-
sequently, TSC21020F systems can be built using slower and therefore less expensive
memory chips.
The program sequencer includes a high performance, selective instruction cache that
enables three-bus operation for fetching an instruction and two data values. This two-
way, set-associative cache holds 32 instructions. The cache is selective (only the
instructions whose fetches conflict with program memory data accesses are cached), so
the TSC21020F can perform a program memory data access and can execute the cor-
responding instruction in the same cycle. The program sequencer fetches the instruction
from the cache instead of from program memory, enabling the TSC21020F to simulta-
neously access data in both program memory and data memory.
Many of the TSC21020F's registers have alternate register sets that can be activated
during interrupt servicing to facilitate a fast context switch. The data registers in the reg-
ister file, DAG registers and the multiplier result register all have alternate sets.
Registers active at reset are called primary registers; the others are called alternate reg-
isters. Bits in the MODE1 control register determine which registers are active at any
particular time.
The primary/alternate select bits for each half of the register file (top eight or bottom
eight registers) are independent. Likewise, the top four and bottom four register sets in
each DAG have independent primary/alternate select bits. This scheme allows passing
of data between contexts.
The TSC21020F has four external hardware interrupts, nine internally generated inter-
rupts, and eight software interrupts. For the external interrupts and the internal timer
interrupt, the TSC21020F automatically stacks the arithmetic status and mode (MODE1)
registers when servicing the interrupt, allowing five nesting levels of fast service for
these interrupts.
An interrupt can occur at any time while the TSC21020F is executing a program. Inter-
nal events that generate interrupts include arithmetic exceptions, which allow for fast
trap handling and recovery.
The programmable interval timer provides periodic interrupt generation. When enabled,
the timer decrements a 32-bit count register every cycle. When this count register
reaches zero, the TSC21020F generates an interrupt and asserts its TIMEXP output.
The count register is automatically reloaded from a 32-bit period register and the count
resumes immediately.
4153H–AERO–04/07