tsc21020f ATMEL Corporation, tsc21020f Datasheet - Page 3

• Manufacturer Part Number: tsc21020f
• Description: Rad. Hard 32/40-bit Ieee Floating Point Dsp
• Manufacturer: ATMEL Corporation

General Description
Independent Parallel
Computation Units
Data Register File
Single-Cycle Fetch of
Instruction and Two
Operands
Memory Interface
Instruction Cache
Hardware Circular
Buffers
Flexible Instruction Set
4153H–AERO–04/07
The TSC21020F is single-chip IEEE floating-point processor optimized for digital signal
processing applications
2100 family of fixed-point DSP processors.
Fabricated in a high-speed, low-power and radiation hard CMOS process, the
TSC21020F has a 50ns instruction cycle time. With a high-performance On-chip instruc-
tion cache, the TSC21020F can execute every instruction in a single cycle.
The TSC21020F features:
The arithmetic/logic unit (ALU), multiplier and shifter perform single-cycle instructions.
The units are architecturally arranged in parallel, maximizing computational throughput.
A single multifunction instruction executes parallel ALU and multiplier operations. These
computation units support IEEE 32-bit single-precision floating-point, extended preci-
sion 40-bit floating-point, and 32-bit fixed-point data formats.
A general-purpose data register file is used for transferring data between the computa-
tion units and the data buses, and for storing intermediate results. This 10-port (16-
register) register file, combined with the TSC21020F's Harvard architecture, allows
unconstrained data flow between computation units and off-chip memory.
The TSC21020F uses a modified Harvard architecture in which data memory stores
data and program memory stores both instructions and data. Because of its separate
program and data memory buses and On-chip instruction cache, the processor can
simultaneously fetch an operand from data memory, an operand from program memory,
and an instruction from the cache, all in a single cycle.
Addressing of external memory devices by the TSC21020F is facilitated by On-chip
decoding of high-order address lines to generate memory bank select signals. Separate
control lines are also generated for simplified addressing of page-mode DRAM. The
TSC21020F provides programmable memory wait states, and external memory
acknowledge controls allow interfacing to peripheral devices with variable access times.
The TSC21020F includes a high performance instruction cache that enables three-bus
operation for fetching an instruction and two data values. The cache is selective-only the
instructions whose fetches conflict with program memory data accesses are cached.
This allows full-speed execution of core, looped operations such as digital filter multiply-
accumulates and FFT butterfly processing.
The TSC21020F provides hardware to implement circular buffers in memory, which are
common in digital filters and Fourier transform implementations. It handles address
pointer wraparound, reducing overhead (thereby increasing performance) and simplify-
ing implementation. Circular buffers can start and end at any location.
The TSC21020F's 48-bit instruction word accommodates a variety of parallel opera-
tions, for concise programming. For example, the TSC21020F can conditionally execute
a multiply, an add, a subtract and a branch in a single instruction.
1.
It is fully compatible with Analog Devices ADSP-21020
(1)
. Its architecture is similar to that of Analog Devices' ADSP-
3