tsc21020f ATMEL Corporation, tsc21020f Datasheet - Page 7

• Manufacturer Part Number: tsc21020f
• Description: Rad. Hard 32/40-bit Ieee Floating Point Dsp
• Manufacturer: ATMEL Corporation

Address Generators and
Program Sequencer
4153H–AERO–04/07
Figure 1. TSC21020F Block Diagram
With a large number of buses connecting the registers to the computation units, data
flow between computation units and from/to off-chip memory is unconstrained and free
from bottlenecks. The 10-port register file and Harvard architecture of the TSC21020F
allow the following nine data transfers to be performed every cycle:
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The processor's 48-bit orthogonal instruction word supports fully parallel data transfer
and arithmetic operations in the same instruction.
Two dedicated address generators and a program sequencer supply addresses for
memory accesses. Because of this, the computation units need never be used to calcu-
late addresses. Because of its instruction cache, the TSC21020F can simultaneously
fetch an instruction and data values from both off-chip program memory and off-chip
data memory in a single cycle.
The data address generators (DAGs) provide memory addresses when external mem-
ory data is transferred over the parallel memory ports to or from internal registers. Dual
data address generators enable the processor to output two simultaneous addresses for
dual operand reads and writes. DAG 1 supplies 32-bit addresses to data memory. DAG
2 supplies 24-bit addresses to program memory for program memory data accesses.
Each DAG keeps track of up to eight address pointers, eight modifiers, eight buffer
length values and eight base values. A pointer used for indirect addressing can be mod-
ified by a value in a specified register, either before (premodify) or after (post-modify)
Off-chip read/write of two operands to or from the register file
Two operands supplied to the ALU
Two operands supplied to the multiplier
Two results received from the ALU and multiplier (three, if the ALU operation is a
combined addition/subtraction).
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