kad5510p Kenet Inc., kad5510p Datasheet - Page 24

• Manufacturer Part Number: kad5510p
• Description: Low Power 10-bit, 250/210/170/125msps Adc
• Manufacturer: Kenet Inc.

ADDRESS 0X74: OUTPUT_MODE_B
ADDRESS 0X75: CONFIG_STATUS
Bit 6 DLL Range
Internal clock signals are generated by a delay-locked loop (DLL),
which has a finite operating range. Table 11 shows the allowable
sample rate ranges for the slow and fast settings.
The output_mode_B and config_status registers are used in
conjunction to enable DDR mode and select the frequency range
of the DLL clock generator. The method of setting these options
is different from the other registers.
The procedure for setting output_mode_B is shown in Figure 39.
Read the contents of output_mode_B and config_status and XOR
them. Then XOR this result with the desired value for
output_mode_B and write that XOR result to the register.
Bit 4 DDR Enable
This bit is set high by default enabling DDR outputs. Do not set
this bit low or invalid output data will result.
Device Test
The KAD5510 can produce preset or user defined patterns on the
digital outputs to facilitate in-site testing. A static word can be
placed on the output bus, or two different words can alternate. In
the alternate mode, the values defined as Word 1 and Word 2 (as
shown in Table 12) are set on the output bus on alternating clock
phases. The test mode is enabled asynchronously to the sample
clock, therefore several sample clock cycles may elapse before
the data is present on the output bus.
OUTPUT_MODE_B
This bit sets the DLL operating range to fast (default)
or slow.
CONFIG_STATUS
This bit sets the output mode to DDR or SDR.
DLL RANGE
Slow
Fast
READ
READ
0x74
0x75
FIGURE 39. SETTING OUTPUT_MODE_B REGISTER
VALUE
000
001
010
100
TABLE 10. OUTPUT FORMAT CONTROL
DESIRED
TABLE 11. DLL RANGES
VALUE
MIN
40
80
24
f
S
MAX
100
MAX
Two’s Complement
OUTPUT FORMAT
Offset Binary
Pin Control
Gray Code
0x93[2:0]
WRITE TO
MSPS
MSPS
0x74
UNIT
KAD5510P
ADDRESS 0XC0: TEST_IO
Bits 7:6 User Test Mode
The four LSBs in this register (Output Test Mode) determine the
test pattern in combination with registers 0xC2 through 0xC5.
Refer to Table 12.
ADDRESS 0XC2: USER_PATT1_LSB AND
ADDRESS 0XC3: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
ADDRESS 0XC4: USER_PATT2_LSB AND
ADDRESS 0XC5: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
48 Pin Package Notes
The KAD5510 is only available in a 48-pin package. While fully
compatible with other family members in the 48-pin package
there are some key differences from the 72-pin package. The 48
pin package option supports LVDS DDR only. A reduced set of pin
selectable functions are available in the 48 pin package due to
the reduced pinout; (OUTMODE, OUTFMT, and CLKDIV pins are
not available). Table 13 shows the default state for these
functions for the 48-pin package. Note that these functions are
available through the SPI, allowing a user to set these modes as
they desire, offering the same flexibility as the 72-pin family
members.
These bits set the test mode to static (0x00) or
alternate (0x01) mode. Other values are reserved.
FUNCTION
OUTMODE
VALUE
0000
OUTFMT
0001
0010
0011
0100
0101
0110
0111
1000
CLKDIV
TABLE 13. 48 PIN SPI - ADDRESSABLE FUNCTIONS
OUTPUT TEST MODE
Negative Full-Scale
Positive Full-Scale
TABLE 12. OUTPUT TEST MODES
Output Driver Mode
Checkerboard
User Pattern
DESCRIPTION
Clock Divider
0xC0[3:0]
One/Zero
Reserved
Reserved
Midscale
Data Coding
Off
user_patt1
WORD 1
0xAAAA
0x8000
0x0000
0xFFFF
0xFFFF
N/A
N/A
Two’s Complement
LVDS, 3mA (DDR)
DEFAULT STATE
Divide by 1
January 3, 2011
user_patt2
WORD 2
0x5555
0x0000
N/A
N/A
N/A
N/A
N/A
FN7693.1