kad5510p Kenet Inc., kad5510p Datasheet - Page 22

• Manufacturer Part Number: kad5510p
• Description: Low Power 10-bit, 250/210/170/125msps Adc
• Manufacturer: Kenet Inc.

Bit 6 LSB First
Bit 5 Soft Reset
Bit 4 Reserved
Bits 3:0 These bits should always mirror bits 4:7 to avoid
ambiguity in bit ordering.
ADDRESS 0X02: BURST_END
If a series of sequential registers are to be set, burst mode can
improve throughput by eliminating redundant addressing. In
3-wire SPI mode the burst is ended by pulling the CSB pin high. If
the device is operated in
2-wire mode the CSB pin is not available. In that case, setting the
burst_end address determines the end of the transfer. During a
write operation, the user must be cautious to transmit the correct
number of bytes based on the starting and ending addresses.
Bits 7:0 Burst End Address
Device Information
ADDRESS 0X08: CHIP_ID
ADDRESS 0X09: CHIP_VERSION
The generic die identifier and a revision number, respectively, can
be read from these two registers.
Indexed Device Configuration/Control
ADDRESS 0X10: DEVICE_INDEX_A
A common SPI map, which can accommodate single-channel or
multi-channel devices, is used for all Intersil ADC products.
Certain configuration commands (identified as Indexed in the SPI
map) can be executed on a per-converter basis. This register
determines which converter is being addressed for an Indexed
command. It is important to note that only a single converter can
be addressed at a time.
This register defaults to 00h, indicating that no ADC is
addressed. Therefore Bit 0 must be set high in order to execute
any Indexed commands. Error code ‘AD’ is returned if any
indexed register is read from without properly setting
device_index_A.
Setting this bit high configures the SPI to interpret
serial data as arriving in LSB to MSB order.
Setting this bit high resets all SPI registers to default
values.
This bit should always be set high.
This register value determines the ending address of
the burst data.
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KAD5510P
ADDRESS 0X20: OFFSET_COARSE AND
ADDRESS 0X21: OFFSET_FINE
The input offset of the ADC core can be adjusted in fine and
coarse steps. Both adjustments are made via an 8-bit word as
detailed in Table 4.
The default value of each register will be the result of the self-
calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register.
ADDRESS 0X22: GAIN_COARSE
ADDRESS 0X23: GAIN_MEDIUM
ADDRESS 0X24: GAIN_FINE
Gain of the ADC core can be adjusted in coarse, medium and fine
steps. Coarse gain is a 4-bit adjustment while medium and fine
are 8-bit. Multiple Coarse Gain Bits can be set for a total
adjustment range of ±4.2% (‘0011’ =~ -4.2% and
‘1100’ =~ +4.2%). It is recommended to use one of the coarse
gain settings (-4.2%, -2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-
tune the gain using the registers at 23h and 24h.
The default value of each register will be the result of the self-
calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register.
Nominal Step Size
–Full Scale (0x00)
Mid–Scale (0x80)
+Full Scale (0xFF)
PARAMETER
0x22[3:0]
Steps
Bit3
Bit2
Bit1
Bit0
TABLE 5. COARSE GAIN ADJUSTMENT
TABLE 4. OFFSET ADJUSTMENTS
+133LSB (+47mV)
1.04LSB (0.37mV)
-133LSB (-47mV)
COARSE OFFSET
0.0LSB (0.0mV)
0x20[7:0]
NOMINAL COARSE GAIN ADJUST
255
+2.8
+1.4
-2.8
-1.4
(%)
0.04LSB (0.014mV)
+5LSB (+1.75mV)
-5LSB (-1.75mV)
FINE OFFSET
0x21[7:0]
0.0LSB
255
January 3, 2011
FN7693.1