kad5510p Kenet Inc., kad5510p Datasheet - Page 23

• Manufacturer Part Number: kad5510p
• Description: Low Power 10-bit, 250/210/170/125msps Adc
• Manufacturer: Kenet Inc.

ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By default,
the tri-level NAPSLP pin can select normal operation or sleep
modes (refer to “Nap/Sleep” on page 18). This functionality can
be overridden and controlled through the SPI. This is an indexed
function when controlled from the SPI, but a global function
when driven from the pin. This register is not changed by a Soft
Reset.
Nap mode must be entered by executing the following sequence:
Return to Normal operation as follows:
Global Device Configuration/Control
ADDRESS 0X71: PHASE_SLIP
When using the clock divider, it’s not possible to determine the
synchronization of the incoming and divided clock phases. This is
particularly important when multiple ADCs are used in a time-
interleaved system. The phase slip feature allows the rising edge
of the divided clock to be advanced by one input clock cycle when
in CLK/4 mode, as shown in Figure 38. Execution of a phase_slip
command is accomplished by first writing a ‘0’ to bit 0 at address
–Full Scale (0x00)
Nominal Step Size
+Full Scale (0xFF)
Mid–Scale (0x80)
TABLE 6. MEDIUM AND FINE GAIN ADJUSTMENTS
PARAMETER
SEQUENCE
SEQUENCE
Steps
1
2
3
4
1
2
3
4
VALUE
000
001
010
100
TABLE 7. POWER-DOWN CONTROL
MEDIUM GAIN
REGISTER
REGISTER
0x23[7:0]
0.016%
0.00%
23
0x10
0x25
0x10
0x25
0x10
0x25
0x10
0x25
+2%
256
-2%
POWER-DOWN MODE
Normal Operation
Sleep Mode
Pin Control
Nap Mode
0x25[2:0]
FINE GAIN
0x24[7:0]
0.0016%
-0.20%
0.00%
+0.2%
VALUE
VALUE
0x01
0x02
0x02
0x02
0x01
0x01
0x02
0x01
256
KAD5510P
SLIP TWICE
71h followed by writing a ‘1’ to bit 0 at address 71h (32 sclk
cycles).
ADDRESS 0X72: CLOCK_DIVIDE
The KAD5510P has a selectable clock divider that can be set to
divide by four, two or one (no division, refer to “Clock Input” on
page 17). This functionality can be controlled through the SPI, as
shown in Table 8. This register is not changed by a Soft Reset.
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output format
of the data, as well as the logical coding. The KAD5510P can
present output data in two physical formats: LVDS or LVCMOS.
Additionally, the drive strength in LVDS mode can be set high
(3mA) or low (2mA). This functionality can be controlled through
the SPI, as shown in Table 9.
Data can be coded in three possible formats: two’s complement, Gray
code or offset binary. This functionality can be controlled through the
SPI, as shown in Table 10.
This register is not changed by a Soft Reset.
SLIP ONCE
FIGURE 38. PHASE SLIP: CLK÷4 MODE, f
CLK÷4
CLK÷4
CLK÷4
CLK
VALUE
000
001
010
100
VALUE
000
001
010
100
TABLE 8. CLOCK DIVIDER SELECTION
TABLE 9. OUTPUT MODE CONTROL
CLK = CLKP – CLKN
1.00ns
4.00ns
CLOCK
CLOCK DIVIDER
Pin Control
Divide by 1
Divide by 2
Divide by 4
0x72[2:0]
Pin Control
LVDS 2mA
LVDS 3mA
0x93[7:5]
LVCMOS
= 1000MHz
January 3, 2011
FN7693.1