tda8358j-n2 NXP Semiconductors, tda8358j-n2 Datasheet - Page 9

• Manufacturer Part Number: tda8358j-n2
• Description: Full Bridge Vertical Deflection Output Circuit In Lvdmos With East-west Amplifier
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Notes
1. To limit V
2. Allowable input range for both inputs: V
3. This value specifies the sum of the voltage losses of the internal current paths between pins V
4. This value specifies the sum of the voltage losses of the internal current paths between pins V
5. The linearity error is measured for a linear input signal without S-correction and is based on the ‘on screen’
6. The linearity errors are specified for a minimum input voltage at pin 1 or pin 2 of 300 mV. Lower input voltages lead
7.
8. Pin FEEDB not connected.
9.
10. V
11. This value specifies the internal voltage loss of the current path between pins V
12. This value specifies the internal voltage loss of the current path between pins OUTEW and EWGND.
13. Measured for R
2002 Sep 25
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
and V
between pins OUTB and GND. Specified for T
between pins OUTA and GND. Specified for T
measurement principle. This method is defined as follows. The output signal is divided in 22 successive equal time
parts. The 1st and 22nd parts are ignored, and the remaining 20 parts form 10 successive blocks k. A block consists
of two successive parts. The voltage amplitudes are measured across R
where V
maximum and average voltages respectively. The linearity errors are defined as:
a)
b)
to voltage dependent S-distortion in the input stage.
a) For I
b) For I
G
G
P(ripple)
v ol
V
input current (see Fig.4) is I
input current (see Fig.4) is I
LE
LE
=
FB
V
------------------------------------------- -
=
=
=
o
o
k
FEEDB
= 500 mV (RMS value); 50 Hz < f
at the first part of the flyback.
OUTA
V
------------------------------------------- -
V
= 100 mA and a voltage of 9 V at R
= 500 mA and a voltage of 21 V at R
and V
V
V
------------------------- -
V
------------------------------ -
INA
FEEDB
OUTA
k
max
V
–
V
avg
–
to 68 V, V
V
–
avg
EWF
k+1
–
V
k
V
–
V
+
–
INB
OUTB
V
are the measured voltages of two successive blocks. V
min
1
V
= 10 k ; R
OUTB
OUTB
100%
100%
FB
must be 66 V due to the voltage drop of the internal flyback diode between pins OUTA
(adjacent blocks)
EWL
i
i
(non adjacent blocks)
= 300 A.
= 350 A.
= 30 ; V
I(bias)
P(ripple)
+ V
o
EWL
EWL
j
j
= 6 V.
= 125 C. The temperature coefficient for V
= 125 C. The temperature coefficient for V
i
< 1 kHz; measured across R
< 1600 mV and V
connected to the line output transformer, the east-west amplifier
connected to the line output transformer, the east-west amplifier
9
I(bias)
M
, starting at k = 1 and ending at k = 10,
V
min
i
> 100 mV.
, V
M
.
FB
max
and OUTA.
and V
avg
loss(1)
loss(2)
are the minimum,
Product specification
P
P
and OUTA, and
and OUTB, and
is a positive value.
is a positive value.
TDA8358J