tda8004at-c1 NXP Semiconductors, tda8004at-c1 Datasheet - Page 6

• Manufacturer Part Number: tda8004at-c1
• Description: Ic Card Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
TDA8004AT_3
Product data sheet
8.2 Voltage supervisor
8.3 Clock circuitry
This block surveys the V
used internally for maintaining the IC in the inactive mode during powering up or powering
down of V
As long as V
on the command lines. This also lasts for the duration of t
higher than V
The system controller should not attempt to start an activation sequence during this time.
When V
The clock signal (CLK) to the card is either derived from a clock signal input on pin XTAL1
or from a crystal up to 26 MHz connected between pins XTAL1 and XTAL2.
The frequency may be chosen at f
CLKDIV2.
The frequency change is synchronous, which means that during transition, no pulse is
shorter than 45 % of the smallest period and that the first and last clock pulse around the
change has the correct width.
In the case of f
In order to reach a 45 % to 55 % duty factor on pin CLK the input signal on XTAL1 should
have a duty factor of 48 % to 52 % and transition times of less than 5 % of the input signal
period.
If a crystal is used with f
on the layout and on the crystal characteristics and frequency.
In the other cases, it is guaranteed between 45 % and 55 % of the period.
The crystal oscillator runs as soon as the IC is powered-up. If the crystal oscillator is used,
or if the clock pulse on XTAL1 is permanent, then the clock pulse will be applied to the
card according to the timing diagram of the activation sequence (see
If the signal applied to XTAL1 is controlled by the microcontroller, then the clock pulse will
be applied to the card by the microcontroller after completion of the activation sequence.
Fig 3. Alarm as a function of V
DD
(internal signal)
DD
falls below V
ALARM
DD
(see
th2
V
XTAL
DD
is less than V
+ V
Figure
, the duty factors are dependent on the signal at XTAL1.
hys(th2)
Rev. 03 — 9 February 2006
th2
XTAL
DD
3).
.
, a deactivation sequence of the contacts is performed.
supply. A defined reset pulse of approximately 10 ms (t
, the duty factor on pin CLK may be 45 % to 55 % depending
th2
DD
+ V
XTAL
(t
hys(th2)
W
= 10 ms)
,
1
2
t
W
f
, the IC will remain inactive whatever the levels
XTAL
,
1
4
f
XTAL
or
W
1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
t
8
after V
W
f
XTAL
TDA8004AT
via pins CLKDIV1 and
DD
V
V
Figure
has reached a level
th2
th2
IC card interface
+ V
hys(th2)
fce660
5).
W
6 of 25
) is