tda8755t NXP Semiconductors, tda8755t Datasheet - Page 8

• Manufacturer Part Number: tda8755t
• Description: Yuv 8-bit Video Low-power Analog-to-digital Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Notes
1. Low frequency ramp signal (V
2. The input conditions are related as follows:
3. Supply voltage ripple rejection:
4. Full-scale sinewave (f
5. The number of effective bits is measured using a 20 MHz clock frequency. This value is given for a 4.43 MHz input
6. Output data acquisition is available after the maximum delay time of t
7. U and V output data is not valid during t
1995 Mar 09
Timing (f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
ds
h
d
dZH
dZL
dHZ
dLZ
r
f
su
h
r
f
CLP
YUV 8-bit video low-power
analog-to-digital interface
SYMBOL
(V
a) Y channel: V
b) U/V channel: V
a) SVRR1 is the variation of the input voltage producing output code 127 (code 15) for supply voltage variation
b) SVRR2 is the relative variation of the full-scale range of analog input for a supply voltage variation of 0.5 V:
frequency on the Y channel (1.5 MHz on the U and V channels). This value is obtained via a Fast Fourier Transform
(FFT) treatment taking 4
harmonics and noise up to half of the clock frequency (NYQUIST frequency).
Conversion to signal-to-noise ratio: S/N = EB
I(p-p)
of 0.5 V:
SVRR1
SVVR2
clk
= 0.25 full-scale, f
= 20 MHz); note 6; see Figs 3 to 7
sampling delay time
output hold time
output delay time
3-state output delay time
3-state output delay time
3-state output delay time
3-state output delay time
clock rise time
clock fall time
HREF set-up time
HREF hold time
data output rise time
data output fall time
minimum time for active clamp
=
=
20 log
------------------------------------------------
I(p-p)
V
V
I(p-p)
I 0
I 0
= 1.0 V; f
--------------------- -
i
PARAMETER
–
= 4.43 MHz for Y and f
= 1.0 V; f
V
–
V
V
i
I 127
V
CCA
= maximum permitted frequency) at the input.
I 255
I 255
T
clk
I(p-p)
i
= 4.43 MHz
(clock periods) acquisition points per period. The calculation takes into account all
i
= 1.5 MHz.
= full-scale and 64 s period) combined with a sinewave input voltage
----------------- -
V
1
CCA
CLP
.
i
= 1.5 MHz for U and V; f
6.02 + 1.76 dB.
enable-to-HIGH
enable-to-LOW
disable-to-HIGH
disable-to-LOW
note 7; see Fig.9
CONDITIONS
8
d
.
clk
= 20 MHz).
7
3
3
7
3
3
MIN.
1
33
10
10
8
4
5
5
12
16
TYP.
Product specification
42
14
14
11
6
MAX.
TDA8755
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
UNIT