tda8757c NXP Semiconductors, tda8757c Datasheet - Page 20

• Manufacturer Part Number: tda8757c
• Description: Tda8757c Triple 8-bit Adc 205 Msps
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 10111
Preliminary data
9.1.4 Control register
Pins SW1 (pin 130) and SW2 (pin 129) are controlled by the I
external devices such as Video Switch by setting bits SW1 and SW2 respectively in
register FINEG.
COAST and HSYNC signals can be derived by setting the I
and ‘Hlevel’ respectively. When bits ‘Vlevel’ and ‘Hlevel’ are set to zero, COAST and
HSYNC are active HIGH.
Bit ‘Edge’ defines the rising or falling edge of CKREF to synchronize the PLL. It will
be on the rising edge if the bit is a logic 0 and on the falling edge if the bit is at logic 1.
Bits ‘Up’ and ‘Do’ are used for the test, to force the charge pump current. These bits
have to be logic 0 during normal use.
Bit ‘Cken’ is used for the test to check the CKADC internal signal. This bit has to be
logic 0 during normal use.
Bits ‘Ip0’, ‘Ip1’ and ‘Ip2’ control the charge pump current, to increase the bandwidth of
the PLL, as shown in
Table 8:
The default programmed value is as follows:
Ip2
0
0
0
0
1
1
1
1
•
•
•
•
Charge pump current = 700 A
Bits ‘Up’ and ‘Do’ are used for testing, normally they are set to logic 0
Rising edge of CKREF: bit ‘Edge’ at logic 0
COAST and HSYNC inputs are active HIGH: bits ‘Vlevel’ and ‘Hlevel’ at logic 0.
Charge pump current control
Rev. 01 — 14 August 2002
Table
Ip1
0
0
1
1
0
0
1
1
8.
Ip0
0
1
0
1
0
1
0
1
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Triple 8-bit ADC 205 Msps
2
C-bus control bits ‘Vlevel’
2
C-bus and command
TDA8757C
Current ( A)
6.25
12.5
25
50
100
200
400
700
20 of 38