tda8757c NXP Semiconductors, tda8757c Datasheet - Page 17

• Manufacturer Part Number: tda8757c
• Description: Tda8757c Triple 8-bit Adc 205 Msps
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9. I
Table 4:
9397 750 10111
Preliminary data
Function
name
SUBADDR
OFFSETR X
COARSER X
FINER
OFFSETG X
COARSEG X
FINEG
OFFSETB
COARSEB X
Fig 8. Timing diagram; CKREFO; Dmx = 0.
2
C-bus and 3W-bus interfaces
I
2
Subaddress
A7 A6 A5 A4 A3 A2 A1 A0 MSB
X
X
X
C-bus and 3W-bus registers
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
9.1 Register definitions
X
X
X
X
X
X
X
X
If an external clock is used, it has to be connected to pin CKEXT. Bit ‘Ckext’ and
bit ‘Ckrs’ in the phase register have to be set at logic 1. It is also important to
disconnect the internal PLL by using the following settings:
There is a delay (t
corresponding output on pin CKREFO; see
t
t
t
The configuration of the registers is given in
CKREFO
CKAO
CLK(buffer)
•
•
0
0
0
0
0
0
0
0
Set bit ‘Do’ in the control register to logic 1.
Set bits ‘Vco1’ and ‘Vco0’ in register VCO to logic 0.
CKREFO
CKREFO
Ckrp = 0
Ckrp = 1
CKADC
CKREF
0
0
0
0
1
1
1
1
= t
= either t
CLK(buffer)
0
0
1
1
0
0
1
1
= tbf and t
0
1
0
1
0
1
0
1
CKAO
Bit definition
X
Or7
Or8
PWD
Og7
Og8
SW2
Ob7
Ob8
+ t
Rev. 01 — 14 August 2002
CKREFO
phase selector
phase selector
(if clock phase >01000) or t
X
Or6
Cr6
Testvol Testvoh Fr4
Og6
Cg6
SW1
Ob6
Cb6
) between the input signal on pin CKREF and the
8 clock periods
=
X
Or5
Cr5
Og5
Cg5
Slevel
Ob5
Cb5
---------------
phase
2
Mode Sa3
Or4
Cr4
Og4
Cg4
Fg4
Ob4
Cb4
Figure
T
t CKAO
Table
CLK pixel
Or3
Cr3
Fr3
Og3
Cg3
Fg3
Ob3
Cb3
t CKREFO
CKAO
FCE699
4.
8.
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Sa2
Or2
Cr2
Fr2
Og2
Cg2
Fg2
Ob2
Cb2
+ T
Triple 8-bit ADC 205 Msps
CLK(pixel)
Sa1
Or1
Cr1
Fr1
Og1
Cg1
Fg1
Ob1
Cb1
TDA8757C
(if phase <01000)
LSB
Sa0
Or0
Cr0
Fr0
Og0
Cg0
Fg0
Ob0
Cb0
Default
value
XXX1 0000
0111 1111
0010 0000
0000 0000
0111 1111
0010 0000
0000 0000
0111 1111
0010 0000
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