cs5461 Cirrus Logic, Inc., cs5461 Datasheet - Page 36

• Manufacturer Part Number: cs5461
• Description: Single-phase, Bidirectional Power/energy Ic
• Manufacturer: Cirrus Logic, Inc.

7.9 Power Offset Register
7.10 Status Register and Mask Register
36
MSB
-(2
Address:
0
Default** = 0.000
This offset value is added to each power value that is computed for each voltage/current sample pair before
being accumulated in the Energy Register. This register can be used to offset contributions to the energy result
that are caused by undesirable sources of energy that are inherent in the system. This value is in two’s comple-
ment notation.
Address:
Default** = 0x000000 (Status Register)
The Status Register indicates the condition of the chip. In normal operation writing a '1' to a bit will cause the bit
to go to the '0' state. Writing a '0' to a bit will maintain the status bit in its current state. With this feature the user
can simply write to the Status Register to clear the bits that have been seen, without concern of clearing any
newly set bits. Even if a status bit is masked to prevent an interrupt, the status bit will still be set in the Status
Register.
The Mask Register is used to control the activation of the INT pin. Placing a logic '1' in the Mask Register will
allow the corresponding bit in the Status Register to activate the INT pin when the status bit is asserted.
IOR
DRDY
DRDY
EOUT
EDIR
)
23
15
7
2
-1
0x000000 (Mask Register)
2
14
-2
EOUT
15 (Status Register); 26 (Mask Register)
IROR
22
14
dicate the end of computation cycles. When running calibrations, this bit indicates the end of a
calibration sequence.
and so this register will be cleared, and one pulse will be generated on the EOUT pin (if en-
abled). If EOUT is asserted, this bit will be cleared automatically just after the beginning of any
subsequent A/D conversion cycle in which no EOUT pulses need to be issued. The bit can also
be cleared by writing to the Status Register. This status bit is set with a maximum frequency of
4 kHz (when MCLK/K is 4.096 MHz). When MCLK/K is not equal to 4.096 MHz, the user should
scale the pulse-rate would be expected with MCLK/K = 4.096 MHz by a factor of 4.096 MHz /
(MCLK/K), to get the actual pulse-rate.
behavior of the EDIR status bit is similar to the EOUT status bit.
too small to fit in the Instantaneous Current Register.
Data Ready. When running in single or continuous conversion acquisition mode, this bit will in-
Indicates that the energy limit has been reached for the EOUT Energy Accumulation Register,
Set whenever the EOUT bit is asserted as long as the energy result is negative. Reset/Clear
Current Out of Range. Set when the magnitude of the calibrated current value is too large or
6
2
-3
2
-4
VROR
EDIR
21
13
5
2
-5
2
-6
CRDY
VOD
20
12
4
2
-7
.....
EOOR
IOD
19
11
3
2
-17
2
-18
LSD
18
10
2
2
-19
2
-20
VSAG
IOR
17
9
1
2
-21
CS5461
2
-22
DS546F2
VOR
16
IC
8
0
LSB
2
-23