cs5461 Cirrus Logic, Inc., cs5461 Datasheet - Page 34

• Manufacturer Part Number: cs5461
• Description: Single-phase, Bidirectional Power/energy Ic
• Manufacturer: Cirrus Logic, Inc.

7.2 DC Current Offset Register and DC Voltage Offset Register
7.3 AC/DC Current Gain Register and AC/DC Voltage Gain Register
7.4 Cycle Count Register
34
MSB
MSB
MSB
-(2
2
2
23
1
Address: 1 (DC Current Offset Register); 3 (DC Voltage Offset Register)
0
Default** = 0.000
The DC Offset Registers are initialized to zero on reset, allowing for uncalibrated normal operation. If DC Offset
Calibration is performed, this register is updated after one computation cycle with the current or voltage offset if
the proper DC input signals are applied. DRDY will be asserted at the end of the calibration. This register may
be read and stored for future system offset compensation. The value is in the range ± full scale. The numeric
format of this register is two’s complement notation.
Address: 2 (Current Gain Register); 4 (Voltage Gain Register)
Default** = 1.000
The Gain Registers are initialized to 1.0 on reset, allowing for uncalibrated normal operation. The Gain registers
hold the result of either the AC or DC gain calibrations, whichever was most recently performed. If DC calibration
is performed, the register is updated after one computation cycle with the system gain when the proper DC input
is applied. If AC calibration is performed, then after ~(6N + 30) A/D conversion cycles (where N is the value of
the Cycle-Count Register) the register(s) is updated with the system gain when the proper AC input is applied.
DRDY will be asserted at the end of the calibration. The register may be read and stored for future system gain
compensation. The value is in the range 0.0 ≤ Gain < 3.9999.
iCPU
K[3:0]
Address: 5
Default** = 4000
The Cycle Count Register value (denoted as ‘N’) determines the length of one energy and RMS computation
cycle. During continuous conversions, the computation cycle frequency is (MCLK/K)/(1024∗N).
)
2
2
2
22
-1
0
2
2
2
21
-2
-1
0 = High-pass filter disabled (default)
1 = High-pass filter enabled
are sampled, the logic driven by CPUCLK should not be active during the sample edge.
0 = normal operation (default)
1 = minimize noise when CPUCLK is driving rising edge logic
clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range be-
tween 1 and 16. Note that a value of “0000” will set K to 16 (not zero).
Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals
Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal
2
2
2
20
-3
-2
2
2
2
19
-4
-3
2
2
2
18
-5
-4
2
2
2
17
-6
-5
2
2
2
16
-7
-6
.....
.....
.....
2
2
2
-17
-16
6
2
2
2
-18
-17
5
2
2
2
-19
-18
4
2
2
2
-20
-19
3
2
2
2
-21
-20
2
CS5461
2
2
2
-22
-21
1
DS546F2
LSB
LSB
LSB
2
2
2
-23
-22
0