cs5461 Cirrus Logic, Inc., cs5461 Datasheet - Page 23

• Manufacturer Part Number: cs5461
• Description: Single-phase, Bidirectional Power/energy Ic
• Manufacturer: Cirrus Logic, Inc.

5. ENERGY PULSE OUTPUTS
5.1 Pulse-Rate Output (EOUT and EDIR)
EOUT and EDIR pins provide pulses which repre-
sent a predetermined magnitude of energy. With
MCLK = 4.096 MHz, and default settings, the
pulses will have an average frequency equal to the
frequency setting in the PulseRateE Register when
the input signals into the voltage and current chan-
nels cause full-scale readings in the Instantaneous
Voltage and Current Registers. When MCLK/K is
not equal to 4.096 MHz, the user should scale the
pulse-rate by a factor of 4.096 MHz / (MCLK / K)
to get the actual output pulse-rate.
5.2 Pulse Output for Normal Format,
Stepper Motor Format and Mechanical
Counter Format
EOUT and EDIR pins can be set in three different
output formats. The default setting is normal output
pulse format. When the pulse is set to either of the
other two formats, the time duration and/or the rel-
ative timing of the EOUT and EDIR pulses is var-
ied such that the pulses can drive either an
electro-mechanical counter or a stepper motor. The
ability to set the pulse output format to one of the
three available formats is controlled by setting cer-
tain bits in the Control Register.
5.2.1 Normal Format
In Normal format the EOUT and EDIR pulse out-
put format is illustrated in Figure 10. These are ac-
DS546F2
EOUT
EDIR
Figure 10. Time-plot representation of pulse output for a typical burst of pulses (Normal For-
. . .
. . .
t
Positive Energy Burst
tive-low pulses of short duration. A positive energy
pulse is represented by a pulse on the EOUT pin
while the EDIR will remain high. A negative ener-
gy pulse is represented by synchronous pulses on
both the EOUT pin and the EDIR pin.
The pulse duration is an integer multiple of MCLK
cycles, approximately equal to 1/16 of the period of
the contents of the Pulse-Rate Register. However
for Pulse-Rate Register settings less than the sam-
pling rate (which is [MCLK/8]/1024), the pulse du-
ration remains constant and is equal to the duration
of the pulses when the Pulse-Rate Register is set to
[MCLK/K]/1024. The maximum pulse frequency
from the EOUT pin is therefore [MCLK / K] / 8.
When DCLK is not equal to 4.096 MHz, the pulse
duration can be predicted by using the pulse dura-
tion values in Table RR and dividing them by
(MCLK/K) / 4.096 MHz.
In Normal pulse output format, the number of puls-
es depends on the value of the PulseRateE Register
and on the amount of energy registered over the
most recent A/D sampling period. A running total
of the energy accumulation is maintained in an in-
ternal register inside the CS5461 (not available to
the user). After each A/D conversion cycle, the re-
sult in the Power Register is multiplied by the value
in the PulseRateE Register, and also by the value in
the TBC (Time-Base Calibration) Register, and
then added to this internal energy accumulation
register. Once a certain amount of positive or neg-
Negative Energy Burst
. . .
. . .
CS5461
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