adc1610s125 NXP Semiconductors, adc1610s125 Datasheet - Page 23

• Manufacturer Part Number: adc1610s125
• Description: Single 16-bit Adc 125 Msps Cmos Or Lvds Ddr Digital Outputs
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1610S125_1
Objective data sheet
Fig 25. SPI mode timing
SCLK
SDIO
CS
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
11.7.2 Default modes at start-up
During circuit initialization, it does not matter which output data standard has been
selected. At power-up, the device defaults to PIN control mode.
A falling edge on CS will trigger a transition to SPI control mode. When the ADC1610S
enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by
the level on pin SDIO (see
can be changed via bit LVDS/CMOS
When the ADC1610S enters SPI control mode, the output data format (2’s complement or
offset binary) is determined by the level on pin SCLK (grey code can only be selected via
the SPI). Once in SPI control mode, the output data format can be changed via bit
DATA_FORMAT in
Fig 26. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR
Fig 27. Default mode at start-up: SCLK HIGH = 2’s complement; SDIO LOW = CMOS
Instruction bytes
(CMOS LVDS DDR)
(CMOS LVDS DDR)
Table
SDIO
SDIO
CS
CS
Rev. 01 — 28 May 2009
21.
Figure
A0 D7 D6 D5 D4 D3 D2 D1
26). Once in SPI control mode, the output data standard
in
Table 21
Register N (data)
.
Offset binary, LVDS DDR
default mode at startup
2's complement, CMOS
default mode at startup
D0 D7 D6 D5 D4
ADC1610S125
Single 16-bit ADC 125 Msps
Register N + 1 (data)
© NXP B.V. 2009. All rights reserved.
005aaa064
005aaa063
D3 D2 D1 D0
005aaa062
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