adc1610s125 NXP Semiconductors, adc1610s125 Datasheet
adc1610s125
Available stocks
Related parts for adc1610s125
adc1610s125 Summary of contents
Page 1
... ADC1610S125 Single 16-bit ADC 125 Msps CMOS or LVDS DDR digital outputs Rev. 01 — 28 May 2009 1. General description The ADC1610S is a single channel 16-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at a sample rate of 125 Msps. ...
Page 2
... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number f (Msps) Package s ADC1610S125HN/C1 125 5. Block diagram INM Fig 1. Block diagram ADC1610S125_1 Objective data sheet Name Description HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 ADC1610S ERROR CORRECTION AND ...
Page 3
... I clock input 13 I complementary clock input 14 O regulator decoupling node 15 I power-down, active HIGH; output enable, active LOW 16 O out-of-range Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps ADC1610S 6 HVQFN40 Transparent top view Pin configuration with LVDS/DDR digital outputs selected © ...
Page 4
... D4 and D5 multiplexed, true 29 O differential output data D2 and D3 multiplexed, complement 30 O differential output data D2 and D3 multiplexed, true 31 O differential output data D0 and D1 multiplexed, complement Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps © NXP B.V. 2009. All rights reserved ...
Page 5
... Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps Min <tbd> <tbd> <tbd> DDA DDO ...
Page 6
... <tbd> OH 3-state; output level = 0 V 3-state; output level = V high impedance HIGH Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps = 5 pF; min. and max. values are across the full dBFS; internal reference mode; INP INM Min Typ 2 ...
Page 7
... INP INM peak-to-peak output input guaranteed no missing codes 100 mV (p- Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps = 5 pF; min. and max. values are across the full dBFS; internal reference mode; INP INM Min Typ AGND - 0 ...
Page 8
... MHz MHz MHz MHz 170 MHz i Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps = 5 pF; min. and max. values are across the full dBFS; internal reference mode; INP INM Min Typ Max - ...
Page 9
... amb Conditions data to SCLKH CS to SCLKH data to SCLKH CS to SCLKH Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps = 5 pF; min. and max. values are across the full dBFS; unless otherwise specified. INP INM ...
Page 10
... Operating mode selection via pin PWD/OE Operating mode Power-down Sleep Power-up Power-up 21) or using pin ODS in PIN control mode. LVDS DDR is selected when ODS is Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps SPI control mode Data Format offset binary R ...
Page 11
... DFS in PIN control mode (offset ) on pins INP and INM set to 0.5V I(cm) Package ESD 8 INP 7 INM Input sampling circuit Figure 6 Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps . DDA Section 11.3 and Table 20 further details). Figure 5. Parasitics Switch Ron = 14 ...
Page 12
... ADT1-1WT 100 nF 100 nF lnput 100 nF 100 nF 100 nF Single transformer configuration suitable for baseband applications Figure 8 is recommended for high frequency applications. In Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps INP C INM 005aaa073 INP ...
Page 13
... Dual transformer configuration suitable for high frequency application REFERENCE AMP BUFFER SELECTION LOGIC Single transformer configuration suitable for baseband applications Table 12. Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps 12 INP 50 8 INM VCM 100 nF 005aaa045 Figure 9 ...
Page 14
... Fig 11. Internal reference (p-p) full scale REFT V REFB VDDA 005aaa049 Fig 13. External reference (p-p) full scale Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps VREF pin full scale (p-p) 330 pF capacitor AGND 1 V external voltage between [1] 0 ...
Page 15
... PACKAGE ESD PARASITICS 1.5 V VCM 0.1 F I(cm) for optimal performance and should always be between 0.9 V and 2 V. Figure 15 illustrates how the SFDR and SNR characteristics vary with Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps full scale (p- 1.78 V 1.59 V 1.42 V 1. ...
Page 16
... Objective data sheet dB SFDR (x MHz) SNR (x MHz) 0.9 V I(cm) CLKP CLKM LVCMOS Clock lnput CLKP Sine Clock lnput CLKM Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps I(cm) 005aaa052 CLKP CLKM 005aaa053 CLKP CLKM 005aaa054 © NXP B.V. 2009. All rights reserved ...
Page 17
... ADC1610S125_1 Objective data sheet LVDS Clock lnput PACKAGE ESD PARASITICS CLKP CLKM Table 19), the circuit can handle signals with duty cycles of Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps CLKP CLKM 005aaa055 Figure 19. The common-mode Vcm(clk) SE_SEL SE_SEL 005aaa056 © ...
Page 18
... Figure to ensure 1 3.4 V compatibility and is isolated from the ADC core. DDO 50 LOGIC DRIVER and is the combination of the an internal resistor and the 21). Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps 20. The buffer is powered by a separate PARASITICS ESD PACKAGE 005aaa112 VDDO Dx ...
Page 19
... P 100 D M AGND Table 29) in order to adjust the output logic voltage and Figure 24 respectively. Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps P 100 RECEIVER M 005aaa123 resistor (typical) at the receiver Figure RECEIVER M 005aaa124 Table 27). When Fast OTR is enabled, OTR © ...
Page 20
... Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps Table 24). A custom test pattern can Table 25 and Table 26) and is selected 2’ ...
Page 21
... DAVP DAVM t clk Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps 13) (N 12 clk 13) (N 12 ...
Page 22
... Number of data bytes to be transferred after the instruction bytes W0 Number of bytes transmitted 0 1 byte 1 2 bytes 0 3 bytes 1 4 bytes or more Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps Table 16 A12 A11 A10 © ...
Page 23
... Table 21 in Table 21. CS SDIO (CMOS LVDS DDR) CS SDIO (CMOS LVDS DDR) Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps Register N (data) Register (data) . Offset binary, LVDS DDR default mode at startup 005aaa063 2's complement, CMOS default mode at startup 005aaa064 © ...
Page 24
... DAVI x2_EN - - - - Reset and operating mode control register (address 0005h) bit description Symbol Access Value SW_RST R R Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps Bit 3 Bit 2 Bit OP_MODE - CLKDIV INTREF_ INTREF EN OUTBUF - DATA_FORMAT DAVINV DAVPHASE - TESTPAT_SEL ...
Page 25
... Access Value LVDS/CMOS R OUTBUF R reserved Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps Description single-ended clock input pin select CLKM CLKP differential/single ended clock input select fully differential single-ended clock input divide by 2 disabled enabled duty cycle stabilizer ...
Page 26
... Offset register (address 0013h) bit description Symbol Access Value R/W 011111 ... 000000 ... 100000 Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps Description output data format offset binary 2’s complement gray code offset binary output clock data valid (DAV) polarity normal inverted ...
Page 27
... R/W 000 001 010 011 100 101 110 111 Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps Description digital test pattern select off mid scale FS +FS toggle ‘1111..1111’/’0000..0000’ custom test pattern ‘1010..1010.’ ‘010..1010’ ...
Page 28
... LVDS DDR output register 2 (address 0022h) bit description Symbol Access Value Description BIT/BYTE_WISE R Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps Description drive strength for DAV CMOS output buffer low medium high very high drive strength for DATA CMOS output buffer ...
Page 29
... Figure 28 w(SCLK) h SCLK SDIO W1 W0 R/W Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps …continued internal termination for LVDS buffer (DAV and DATA) no internal termination 300 180 110 150 100 w(SCLKL) t w(SCLKH) A12 A11 ...
Page 30
... 2.5 scale (1) ( 6.1 4.25 6.1 4.25 4.5 0.5 5.9 3.95 5.9 3.95 REFERENCES JEDEC JEITA MO-220 - - - Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps detail 0.5 4.5 0.05 0.1 0.1 0.05 0.3 EUROPEAN PROJECTION SOT618 ISSUE DATE ...
Page 31
... NXP Semiconductors 13. Revision history Table 31. Revision history Document ID Release date ADC1610S125_1 20090528 ADC1610S125_1 Objective data sheet Data sheet status Change notice Objective data sheet - Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps Supersedes - © NXP B.V. 2009. All rights reserved ...
Page 32
... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 28 May 2009 ADC1610S125 Single 16-bit ADC 125 Msps © NXP B.V. 2009. All rights reserved ...
Page 33
... NXP B.V. 2009. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ADC1610S125 Single 16-bit ADC 125 Msps All rights reserved. Date of release: 28 May 2009 Document identifier: ADC1610S125_1 ...