adc1610s125 NXP Semiconductors, adc1610s125 Datasheet - Page 11

• Manufacturer Part Number: adc1610s125
• Description: Single 16-bit Adc 125 Msps Cmos Or Lvds Ddr Digital Outputs
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1610S125_1
Objective data sheet
11.1.4
11.2.1 Input stage
11.2.2 Anti-kickback circuitry
11.2 Analog inputs
Selecting the output data format
The output data format can be selected via the SPI interface (offset binary, 2’s
complement or gray code; see
binary or 2’s complement). Offset binary is selected when DFS is LOW. When DFS is
HIGH, 2’s complement is selected.
The analog input of the ADC1610S supports a differential or a single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (V
The full scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see
The equivalent circuit of the sample and hold input stage, including ESD protection and
circuit and package parasitics, is shown in
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
Anti-kickback circuitry (R-C filter in
injection generated by the sampling capacitance.
Fig 5.
Input sampling circuit
I(cm)
INM
INP
) on pins INP and INM set to 0.5V
8
7
Rev. 01 — 28 May 2009
Package
Table
Figure 6
21) or using pin DFS in PIN control mode (offset
ESD
Figure
Section 11.3
is needed to counteract the effects of charge
Parasitics
DDA
5.
.
Ron = 14
Ron = 14
internal
internal
Switch
Switch
clock
clock
and
ADC1610S125
Single 16-bit ADC 125 Msps
Table 20
Sampling
Capacitor
Sampling
Capacitor
4 pF
4 pF
005aaa043
further details).
© NXP B.V. 2009. All rights reserved.
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