maxq3180-ran Maxim Integrated Products, Inc., maxq3180-ran Datasheet - Page 40

• Manufacturer Part Number: maxq3180-ran
• Description: Low-power, Multifunction, Polyphase Afe
• Manufacturer: Maxim Integrated Products, Inc.

MAXQ3180 never clears them on its own unless a reset
occurs. The interrupt flags should be cleared by the
master by writing the appropriate register.
The configuration bits OVEN and OCEN allow enable-
or disable-monitoring the overvoltage and overcurrent
events on each phase independently.
The MAXQ3180 detects voltage sag events and can
issue interrupt request signals to the master when
these events occur. The sag level threshold is deter-
mined by the setting of the SAGLVL register. The
SAGLVL register represents the 16 most significant bits
of a raw VRMS register. A voltage sag event is detect-
ed if the RMS-voltage value remains below the SAGLVL
threshold for the number of line cycles specified in the
SAGCYC register. The flags SAGA, SAGB, and SAGC
are set when voltage sag is detected on phase A, B, or
C, respectively. If enabled, any of these flags issues an
interrupt request when they are set to 1.
The MAXQ3180 detects and reports the following tam-
per conditions:
• Missing Potential. The MAXQ3180 detects a miss-
Low-Power, Multifunction, Polyphase AFE
Table 11. Meter to Real Units Conversion
40
ing potential condition if a phase voltage waveform
either has a magnitude less than 10% of the full-
scale range or has no zero crossings, i.e., the entire
waveform lies above or below zero. The MISVF bit is
set in the FLAGS status register for phase A, B, or C
NAME
VFS
IFS
t
NS
FR
______________________________________________________________________________________
Analog scan frame timing. This parameter is defined by the R_ADCRATE setting and
system clock frequency f
Default conditions are R_ADCRATE = 199, f
Number of frames per line cycle. This parameter is defined by nominal line frequency f
and frame timing t
Default conditions are t
Full-scale voltage. This is the input voltage that produces full-scale ADC output: 2048 LSB
for positive or -2048 LSB for negative, total 12-bit range. This parameter is defined by the
hardware voltage transducer ratio V
Default conditions are V
Full-scale current. This is the input current that produces full-scale ADC output: 2048 LSB
for positive or -2048 LSB for negative, total 12-bit range. This parameter is defined by the
hardware current transducer ratio I
Default conditions are V
t
NS = 1/(t
VFS = V
IFS = V
FR
= (R_ADCRATE + 1) x 8/f
Tamper Condition Detection
FR
FSADC
FSADC
FR
:
Voltage Sag Detection
x f
FR
FSADC
FSADC
x I
LINE
SYS
x V
= 200µs, f
TR
TR
:
)
= 1V, V
= 1V, I
TR
TR
LINE
and ADC full-scale input voltage V
TR
TR
and ADC full-scale input voltage V
DESCRIPTION
= 100A/V (for reference meter design).
SYS
= 545V/V (for reference meter design).
= 50Hz.
SYS
= 8MHz.
• Voltage Unbalance. The MAXQ3180 detects a volt-
• Current Unbalance. The MAXQ3180 detects a cur-
All energy calculations, including various threshold
checks, are performed internally in fixed format in
meter units. Therefore, the threshold values must be
supplied by the user in meter units as well. This section
describes how to convert real units (V, A, kWh, etc.)
into meter units and vice versa.
The conversion factors are based on the settings
shown in Table 11, defined by the user’s design.
Meter units are defined with respect to the base para-
meters in Table 11 as shown in Table 12.
to report a missing potential condition. Also, the
MISV flag bit is set in the STATUS1 register, which
can cause an interrupt request signal if enabled.
age unbalance condition if the sum of all three volt-
age signals (e.g., VA + VB + VC) has a magnitude
greater than VUBLVL/2. The VUBLVL register repre-
sents the 16 most significant bits of the raw VRMS
register. The VUNBF flag is set in the STATUS1 reg-
ister to report voltage unbalance. This can cause an
interrupt request signal if enabled.
rent unbalance condition if the sum of current signals
IA + IB + IC has a magnitude greater than IUBLVL/2.
The IUBLVL register represents the 16 most significant
bits of a raw IRMS register. The IUNBF flag is set in
the STATUS1 register to report a current unbalance.
FSADC
Meter Units to Real Units Conversion
FSADC
:
:
LINE
DEFAULT VALUE
200µs/frame
100 frames/
line cycle
545V
100A