maxq3180-ran Maxim Integrated Products, Inc., maxq3180-ran Datasheet - Page 38

• Manufacturer Part Number: maxq3180-ran
• Description: Low-power, Multifunction, Polyphase Afe
• Manufacturer: Maxim Integrated Products, Inc.

programmed to enable and configure this feature. If the
measured E_VA value for a phase (A, B, or C) falls
below the NOLOAD threshold, the energy accumula-
tors for this phase are not incremented. Setting
NOLOAD = 0 disables this feature.
The two pulse output pins, CFP and CFQ, have associ-
ated accumulators PLS1, PLS2 and configurable
thresholds THR1, THR2. The MAXQ3180 issues a pulse
on the output pin when the pulse accumulator exceeds
the threshold level (e.g., PLS1 > THR1), then continues
accumulation from the level PLS1 = PLS1 - THR1.
Each pulse output accumulator can be configured to
include energy accumulators E1, E2, or E3 (typically
corresponding to phase A, B, C) as independent terms,
and to output various quantities, by setting the PLSCFG
register:
Bits [2:0] (nnn) and [10:8] (mmm) specify which
phase(s) are included in the pulse output.
Low-Power, Multifunction, Polyphase AFE
Table 9. Pulse Output Configuration
Table 10. Pulse Output Quantity Selection
38
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PLSCFG = (qqqqqmmm ppppppnnn) binary
nnn BITS
ppppp OR qqqqq
000
001
010
011
100
101
110
111
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
Energy Pulse Output
PLS1 INCLUDE
E1 + E2 + E3
E1 + E2
E1 + E3
E2 + E3
E1
E2
E3
0
ACCUMULATED VALUE
R1 + R2 + R3 + R4
R1 + R2 - R3 - R4
AP + AN
AP - AN
V
I
RMS
AN
VA
AP
RMS
IH
Bits [7:3] (ppppp) specify the quantity that is directed
into the pulse 1 output; bits [15:11] (qqqqq) specify the
quantity that is directed into the pulse 2 output.
Both PLS1 and PLS2 accumulators accumulate only
absolute values of selected quantity. If the selected
pulse-output quantity changes sign, the PLS1 or PLS2
accumulator is cleared and starts accumulation over.
The REV_P (reverse power) bit is set in the STATUS2
register if the PLS1 input stays negative for REV_TIMO
consecutive line cycles; the bit is cleared when the
PLS1 input stays positive for REV_TIMO consecutive
line cycles. Additionally, the direction change DCH_P
status bit is set whenever the direction bit REV_P
changes its state. The DCH_P bit causes an interrupt
request to the master if enabled (unmasked).
Similarly, the REV_Q bit is set in the STATUS2 register if the
PLS2 input stays negative for REV_TIMO consecutive line
cycles; the bit is cleared when the PLS2 input stays posi-
tive for REV_TIMO consecutive line cycles. Additionally,
the DCH_Q status bit is set whenever the direction bit
REV_Q changes its state. The DCH_Q bit causes an inter-
rupt request to the master if enabled (unmasked).
mmm BITS
000
001
010
011
100
101
110
111
True active energy (may be negative)
Absolute active energy
True reactive energy (may be negative)
Absolute reactive energy
Apparent energy
Amp-hours
I
V
Active positive energy
Active negative energy
RMS
RMS
(for calibration purposes)
(for calibration purposes)
DESCRIPTION
PLS2 INCLUDE
E1 + E2 + E3
E1 + E2
E1 + E3
E2 + E3
E1
E2
E3
0