maxq3180-ran Maxim Integrated Products, Inc., maxq3180-ran Datasheet - Page 35

• Manufacturer Part Number: maxq3180-ran
• Description: Low-power, Multifunction, Polyphase Afe
• Manufacturer: Maxim Integrated Products, Inc.

Filter coefficient (lpf_b0fns) is a signed 16-bit value and
can be configured by the master. In the previous equa-
tion, Y denotes the global NS value, and X denotes
individual NS measurements produced by zero-cross-
ing events detected on phase A, B, or C voltage chan-
nel. Note that if all three phase voltages are present,
the filter above receives three inputs each line cycle.
The global NS value is used to generate line-cycle trig-
ger for DSP processing. Note that value NS can be
configured by the master, which may be necessary if
all three voltage signals are lost and no zero crossings
are detected. The line period is then calculated as a
product of NS and the scan slot period t
timing calibration register TIME_FS). The reciprocal of
this value is the line frequency, which can be obtained
as a fixed-point value with 1 LSB = 0.001Hz by reading
the virtual register LINEFREQ.
The MAXQ3180 monitors the voltage signal on each
phase for zero-crossing events. If no ascending zero
crossings are detected within a specified number of
analog scan frame periods, the NOZC (STATUS1.11)
flag is set by the MAXQ3180 to notify the master of this
condition. If the interrupt enable bit INT_MASK.11 is set
to 1, the interrupt signal IRQ is driven low by the
MAXQ3180 whenever NOZC = 1. The master can clear
NOZC back to 0 to remove the interrupt condition.
A phase sequence error occurs when zero-crossing
events occur on all three phases, but they do not occur
in the expected order. Normally, a zero-crossing event
should occur on the phase A voltage signal, followed
by phase B, phase C, and then phase A again. If a zero
crossing on phase A is then followed immediately by a
zero crossing on phase C (and not by phase B as
expected), this is registered by the MAXQ3180 as a
phase sequence error.
When a phase sequence error occurs, the MAXQ3180
sets the phase sequence error flag SEQERR
(STATUS1.15) to 1. If the corresponding interrupt
enable bit (INT_MASK.15) is also set to 1, the interrupt
signal IRQ is driven low by the MAXQ3180 whenever
SEQERR = 1. The master can clear SEQERR back to 0
to remove the interrupt condition.
For each of the three phases, the MAXQ3180 calcu-
lates RMS voltage and RMS current values, as well as
determines active and reactive energy, using a line-
cycle-based integration process.
RMS Voltage, RMS Current, and Energy Calculation
Y
n
= Y
n-1
Low-Power, Multifunction, Polyphase AFE
+ (lpf_b0fns/65,536) x (X
______________________________________________________________________________________
No-Zero-Crossing Detection
Phase Sequence Errors
C
n
(stored in the
- Y
n-1
)
The power, energy, and RMS calculation process con-
sists of two tasks: continuous accumulation and post-
processing triggered every CYCNT line cycles. The
accumulation task accumulates raw data obtained from
the AFE during CYCNT line cycles. This task is per-
formed continuously in the background by the
MAXQ3180. When a CYCNT line cycles accumulation
stage has completed, which is determined by a dedi-
cated frame counter exceeding the CYCNT x NS level,
the raw integral accumulator values are saved for post-
processing and cleared, beginning the next cycle of
accumulation task. Then, the DSP postprocessing is
triggered to process saved integrals and calculate
energy, power, etc., values. Note that the background
accumulation task continues while foreground postpro-
cessing is taking place, i.e., both tasks are executed
simultaneously sharing CPU time. It is essential that the
DSP postprocessing calculations be completed before
the next DSP trigger to avoid losing accumulated data.
The master should allow enough processing time by
adjusting the R_ADCRATE register. Default settings
provide plenty of CPU time for both tasks.
The MAXQ3180 accumulates raw sums and calculates
line-cycle integrals for each voltage-current pair sepa-
rately. The individual power accumulators are:
• P1 = (VA x IA)
• P2 = (VB x IB) or -IB x (VA + VC) or -IB x VA
• P3 = (VC x IC)
The P1 and P3 accumulators always operate in a single
mode: (VA x IA) for the P1 accumulator, (VC x IC) for
the P3 accumulator. Alternately, the operating mode of
the P2 accumulator is defined by setting bits 0 and 1 in
the CONNCT register as shown in Table 8.
If the CONNCT bits are set to 01b, then the P2 (phase
B) input voltage sample is calculated using an allpass
filter described as:
Table 8. P2 Power Accumulator Modes
CONNCT[1:0]
10b, 11b
00b
01b
Power Calculation (Active, Reactive, Apparent)
(VA + VC)
(AVC1/2
n
P2 OPERATING
-IB x (VA + VC)
= (AVCO/2
(VB x IB)
-IB x VA
MODE
16
)(VC
16
n-1
)(VC
+ VA
n
5S/13S 3-Wire Delta,
CONFIGURATIONS
8S/15S 4-Wire Delta
9S/16S 4-Wire Wye
6S/14S 4-Wire Wye
+ VA
n
)
WIRING
n-1
) +
35