maxq3180-ran Maxim Integrated Products, Inc., maxq3180-ran Datasheet - Page 24

• Manufacturer Part Number: maxq3180-ran
• Description: Low-power, Multifunction, Polyphase Afe
• Manufacturer: Maxim Integrated Products, Inc.

Low-Power, Multifunction, Polyphase AFE
Table 4. RAM Register Summary (continued)
24
R_ADCRATE
R_ADCACQ
COM_TIMO
ACC_TIMO
REV_TIMO
R_ACFG
R_SPICF
NAME
______________________________________________________________________________________
ADDRESS
(BYTE)
0x07C
0x07E
0x080
0x082
0x084
0x086
0x088
124
126
128
130
132
134
136
Communication
DESCRIPTION
Analog Control
Analog Control
Analog Control
Reverse Pulse
Delay Timeout
Accumulation
SPI Control
Direction
Timeout
Timeout
Shadow
Shadow
Shadow
Shadow
Energy
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DEFAULT
0x000B
0x00C7
VALUE
0x0032
0x03E8
0x0007
0x002F
0x0080
(HEX)
15:8, 5:3
BITS
15:8
15:9
15:7
5:4
8:0
6:0
5:3
7
6
3
2
1
0
7
6
2
1
0
15:0
15:0
15:0
R_ADCRATE
R_ADCACQ
ADCASD
ADCCD
ADCRY
ADCBY
CKPHA
CKPOL
NAME
ADCIE
ARBE
ADCE
ESPII
[1:0]
[8:0]
[6:0]
CHR
SAS
—
—
—
—
—
Number of line cycles to detect
reverse pulse direction
Number of line cycles before
starting energy accumulation
Number of frames to reset
communication channel
These bits are reserved and
should be set to 0
Automatic shutdown disable
Sample ready (system)
ADC clock divider
00: ADC = SYSCLK
01: ADC = SYSCLK/2
10: ADC = SYSCLK/4
11: Reserved
ADC busy (system)
ADC interrupt enable (system)
Internal V
ADC enable
Reserved. Should be set to 0.
Number of SYSCLKs between
two consecutive ADC
conversions minus 1
Reserved. Should be set to 0.
Number of SYSCLKs for amplifier
to acquire input signal before
conversion minus 1
Reserved. Should be set to 0.
SPI interrupt enable (system)
SSEL active level select
These bits are reserved and
should be set to 0
SPI character length bit
SPI clock phase select
SPI clock polarity select
0: SSEL active low
1: SSEL active high
0: 8 bits
1: 16 bits
DESCRIPTION
REF
enable