ADN8102-EVALZ Analog Devices, ADN8102-EVALZ Datasheet - Page 29

• Manufacturer Part Number: ADN8102-EVALZ
• Description: 3.75 Gbps Quad Bidirectional CX4 Equalizer
• Manufacturer: Analog Devices

REGISTER MAP
Table 17. I
Name
Reset
Global
Configuration
Control
Mode
TxHeadroom
IN_A
Configuration
IN_A LOS
Threshold
IN_A LOS
Hysteresis
IN_A LOS
Status
IN_A EQ1
Control
IN_A EQ2
Control
IN_A0 FR4
Control
IN_A1 FR4
Control
IN_A2 FR4
Control
IN_A3 FR4
Control
IN_B
Configuration
IN_B LOS
Threshold
IN_B LOS
Hysteresis
IN_B LOS
Status
IN_B EQ1
Control
IN_B EQ2
Control
IN_B3 FR4
Control
IN_B2 FR4
Control
IN_B1 FR4
Control
IN_B0 FR4
Control
1
1
2
C Register Definitions
Address
0x00
0x02
0x0F
0x23
0x80
0x81
0x82
0x1F
0x83
0x84
0x85
0x8D
0x95
0x9D
0xA0
0xA1
0xA2
0x3F
0xA3
0xA4
0xA5
0xAD
0xB5
0xBD
TxH_B3
Bit 7
STICKY
LOS[3]
STICKY
LOS [3]
Bit 6
TxH_B2
PNSWAP
THRESH[6]
HYST[6]
STICKY
LOS[2]
EQ CTL
SRC
PNSWAP
THRESH[6]
HYST[6]
STICKY
LOS [2]
EQ CTL
SRC
Bit 5
TxH_B1
EQBY
THRESH[5]
HYST[5]
STICKY
LOS[1]
EQ1[5]
EQ2[5]
EQBY
THRESH[5]
HYST[5]
STICKY
LOS [1]
EQ1[5]
EQ2[5]
Rev. A | Page 29 of 32
Bit 4
TxH_B0
EN
THRESH[4]
HYST[4]
STICKY
LOS[0]
EQ1[4]
EQ2[4]
EN
THRESH[4]
HYST[4]
STICKY
LOS[0]
EQ1[4]
EQ2[4]
Bit 3
TxH_A3
THRESH[3]
HYST[3]
REAL-TIME
LOS[3]
EQ1[3]
EQ2[3]
THRESH[3]
HYST[3]
REAL-TIME
LOS[3]
EQ1[3]
EQ2[3]
Bit 2
TxH_A2
EQ[2]
THRESH[2]
HYST[2]
REAL-TIME
LOS[2]
EQ1[2]
EQ2[2]
EQ[2]
THRESH[2]
HYST[2]
REAL-TIME
LOS[2]
EQ1[2]
EQ2[2]
Bit 1
LB[1]
MODE[1]
TxH_A1
EQ[1]
THRESH[1]
HYST[1]
REAL-TIME
LOS[1]
EQ1[1]
EQ2[1]
LUT
SELECT
LUT
SELECT
LUT
SELECT
LUT
SELECT
EQ[1]
THRESH[1]
HYST[1]
REAL-TIME
LOS[1]
EQ1[1]
EQ2[1]
LUT
SELECT
LUT
SELECT
LUT
SELECT
LUT
SELECT
Bit 0
RESET
LB[0]
MODE[0]
TxH_A0
EQ[0]
THRESH[0]
HYST[0]
REAL-TIME
LOS[0]
EQ1[0]
EQ2[0]
LUT
FR4/CX4
LUT
FR4/CX4
LUT
FR4/CX4
LUT
FR4/CX4
EQ[0]
THRESH[0]
HYST[0]
REAL-TIME
LOS[0]
EQ1[0]
EQ2[0]
LUT
FR4/CX4
LUT
FR4/CX4
LUT
FR4/CX4
LUT
FR4/CX4
ADN8102
Default
0x00
0x00
0x00
0x30
0x04
0x12
0x00
0x00
0x00
0x00
0x00
0x00
0x30
0x04
0x12
0x00
0x00
0x00
0x00
0x00
0x00