ADN8102-EVALZ Analog Devices, ADN8102-EVALZ Datasheet - Page 18

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ADN8102-EVALZ

Manufacturer Part Number
ADN8102-EVALZ
Description
3.75 Gbps Quad Bidirectional CX4 Equalizer
Manufacturer
Analog Devices
Datasheet
ADN8102
Loss of Signal/Signal Detect
An independent signal detect output is provided for all eight
input ports of the device. The signal-detect function measures
the low frequency amplitude of the signal at the receiver input
and compares this measurement with a defined threshold level.
If the measurement indicates that the input signal swing is
smaller than the threshold for 250 μs, the channel indicates a
loss-of-signal event. Assertion and deassertion of the LOS signal
occurs within 100 μs of the event.
The LOS-assert and LOS-deassert levels are set on a per channel
basis through the I
IN_B LOS threshold and IN_A/IN_B LOS hysteresis registers,
respectively. The recommended settings are IN_A/IN_B THRESH
= 0x0C and IN_A/IN_B HYST = 0x0D. All ports are factory
tested with these settings to ensure that an LOS event is asserted
for single-ended dc input swings less than 20 mV and is deasserted
for single-ended dc input swings greater than 225 mV.
The LOS status for each individual channel can be accessed
through the I
LOS status can be read from the IN_A/IN_B LOS status registers
(Address 0x1F and Address 0x3F). The four LSBs of each register
represent the current LOS status of each channel, with high
representing an ongoing LOS event. The four MSBs of each
register represent the historical LOS status of each channel,
with high representing a LOS event at any time on a specific
channel. The MSBs are sticky and remain high once asserted
until cleared by the user by overwriting the bits to 0.
Table 8. LOS Threshold and Hysteresis Control Registers
Name
IN_A/IN_B
LOS Threshold
IN_A/IN_B
LOS Hysteresis
Table 9. LOS Status Registers
Name
IN_A/IN_B
LOS Status
2
C control interface. The independent channel
Address
0x1F,
0x3F
Address
0x81,
0xA1
0x82,
0xA2
2
C control interface, by writing to the IN_A/
Bit 7
Bit 7
STICKY
LOS[3]
Bit 6
THRESH[6]
HYST[6]
Bit 6
STICKY
LOS[2]
Bit 5
THRESH[5]
HYST[5]
Bit 5
STICKY
LOS[1]
Rev. A | Page 18 of 32
Bit 4
STICKY LOS [0]
Bit 4
THRESH[4]
HYST[4]
Recommended LOS Settings
Recommended settings for LOS are as follows:
LANE INVERSION
The input P/N inversion is a feature intended to allow the user
to implement the equivalent of a board-level crossover in a much
smaller area and without additional via impedance discontinuities
that degrade the high frequency integrity of the signal path. The
P/N inversion is available on a per port basis and is controlled
through the I
plished by writing to the PNSWAP bit (Bit 6) of the IN_A/IN_B
configuration register (see Table 7) with low representing a
noninverting configuration and high representing an inverting
configuration. Note that using this feature to account for signal
inversions downstream of the receiver requires additional attention
when switching connectivity.
Bit 3
THRESH[3]
HYST[3]
Set IN_A/IN_B THRESH to 0x0C for an assert voltage of
20 mV differential (40 mV p-p differential).
Set IN_A/IN_B HYST to 0x0D for a deassert voltage of
225 mV differential (450 mV p-p differential).
Bit 3
REAL-TIME
LOS[3]
2
C control interface. The P/N inversion is accom-
Bit 2
THRESH[2]
HYST[2]
Bit 2
REAL-TIME
LOS[2]
Bit 1
THRESH[1]
HYST[1]
Bit 1
REAL-TIME
LOS[1]
Bit 0
THRESH[0]
HYST[0]
Bit 0
REAL-TIME
LOS[0]
Default
0x04
0x12

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