ADN8102-EVALZ Analog Devices, ADN8102-EVALZ Datasheet - Page 20

• Manufacturer Part Number: ADN8102-EVALZ
• Description: 3.75 Gbps Quad Bidirectional CX4 Equalizer
• Manufacturer: Analog Devices

ADN8102
TRANSMITTERS
Output Structure and Output Levels
The ADN8102 transmitter outputs incorporate 50 Ω termina-
tion resistors, ESD protection, and an output current switch. Each
port provides control of both the absolute output level and the
pre-emphasis output level. It should be noted that the choice of
output level affects the output common-mode level. A 600 mV
peak-to-peak differential output level with full pre-emphasis
range requires an output termination voltage of 2.5 V or greater
(V
Pre-Emphasis
The total output amplitude and pre-emphasis setting space is
reduced to a single map of basic settings that provides seven
settings of output equalization to ease programming for typical
channels. The PE_A/PE_B[1:0] pins provide selections 0, 2, 4,
and 6 of the seven pre-emphasis settings through toggle pin
control, covering the entire range of settings at lower resolution.
The full resolution of seven settings is available through the I
interface by writing to Bits[2:0] (PE[2:0] of the OUT_A/OUT_B
configuration registers) with I
pin control. Similar to the receiver settings, the ADN8102 allows
joint control of all four channels in a transmit port. Table 11
summarizes the absolute output level, pre-emphasis level, and
high frequency boost for each of the basic control settings and
the typical length of the CX4 cable and FR4 trace that each
setting compensates.
Full control of the transmit output levels is available through the
I
the OUT_A/OUT_B Output Level Control[1:0] registers for the
channel of interest. Table 13 shows the supported output level
settings of the OUT_A/OUT_B Output Level Control[1:0]
registers. Register settings not listed in Table 13 are not
supported by the ADN8102.
Table 11. Transmit Pre-Emphasis Boost and Overshoot vs. Setting
PE
0
1
2
3
4
5
6
1
Table 12. Output Configuration Registers
Name
OUT_A/OUT_B Configuration
OUT_A/OUT_B Output Level Control 1
OUT_A/OUT_B Output Level Control 0
2
These PE settings are also available via external device pins, PE_A[1:0] and PE_B[1:0].
1
1
1
1
C control interface. This full control is achieved by writing to
TTO
, V
CC
Boost (dB)
0
2
3.5
4.9
6
7.4
9.5
≥ 2.5 V).
Overshoot
0%
25%
50%
75%
100%
133%
200%
2
C settings overriding the toggle
DC Swing (mV p-p diff)
800
800
800
800
800
600
400
Address
0xC0, 0xE0
0xC1, 0xE1
0xC2, 0xE2
Bit 7
PE CTL SRC
Rev. A | Page 20 of 32
2
C
Typical CX4 Cable Length (Meters)
0 to 2.5
2.5 to 5
5 to 7.5
7.5 to 10
10 to 12.5
15 to 17.5
20 to 22.5
Bit 6
The output equalization is optimized for less than 1.75 Gbps
operation but can be optimized for higher speed applications at
up to 3.75 Gbps through the I
the DATA RATE bit (Bit 4) of the OUT_A/OUT_B configuration
registers, with high representing 3.75 Gbps and low representing
1.75 Gbps. The PE CTL SRC bit (Bit 7) in the OUT_A/OUT_B
Output Level Control 1 register determines whether the pre-
emphasis and output current controls for the channel of interest
are selected from the optimized map or directly from the OUT_A/
OUT_B Output Level Control[1:0] registers (per channel). Setting
this bit high selects pre-emphasis control directly from the
OUT_A/OUT_B Output Level Control[1:0] registers, and setting
it low selects pre-emphasis control from the optimized map.
Bit 5
EN
VP
V2
Tx SIMPLIFIED DIAGRAM
VC
V3
Bit 4
DATA RATE
OUTx_OLEV1[6:0]
OUTx_OLEV0[6:0]
Figure 40. Simplified Output Structure
V1
VN
I
DC
TERMINATION
+ I
Bit 3
Q1
50Ω
PE
ON-CHIP
RP
Typical FR4 Trace Length (Inches)
0 to 5
0 to 5
10 to 15
10 to 15
15 to 20
20 to 25
25 to 30
2
Q2
C control interface by writing to
Bit 2
PE[2]
I
TOT
RN
50Ω
Bit 1
PE[1]
Bit 0
PE[0]
ESD
Default
0x20
0x40
0x40
VCC
VTTO
OP
ON
VEE