ADN8102-EVALZ Analog Devices, ADN8102-EVALZ Datasheet - Page 16

• Manufacturer Part Number: ADN8102-EVALZ
• Description: 3.75 Gbps Quad Bidirectional CX4 Equalizer
• Manufacturer: Analog Devices

ADN8102
THEORY OF OPERATION
ADDR[1:0]
INTRODUCTION
The ADN8102 is a quad bidirectional cable and backplane
equalizer that provides both input equalization and output pre-
emphasis on both the line card and cable sides of the device.
The device supports full loopback and through connectivity
of the two unidirectional half-links, each consisting of four
differential signal pairs.
The ADN8102 offers extensively programmable output levels
and pre-emphasis as well as the ability to disable the output
current. The receivers integrate a programmable, multizero
equalizer transfer function that is optimized to compensate
either typical backplane or typical cable losses.
The I/O on-chip termination resistors are terminated to user-
settable supplies to support dc coupling in a wide range of logic
styles. The ADN8102 supports a wide core supply range; V
can be set from 1.8 V to 3.3 V. These features, together with
programmable output levels, allow for a wide range of dc- and
ac-coupled I/O configurations.
Ox_A[3:0]
Ix_B[3:0]
LOS_B
RESET
SDA
SCL
LB
PRE-EMPHASIS
EQUALIZATION
Figure 37. Simplified Functional Block Diagram
TRANSMIT
RECEIVE
EQ
PE
CONTROL LOGIC
2:1
ADN8102
2:1
PRE-EMPHASIS
EQUALIZATION
TRANSMIT
RECEIVE
PE
EQ
Ox_B[3:0]
LOS_A
Ix_A[3:0]
EQ_A[1:0]
PE_A[1:0]
EQ_B[1:0]
PE_B[1:0]
ENA
ENB
CC
Rev. A | Page 16 of 32
RECEIVERS
Input Structure and Input Levels
The ADN8102 receiver inputs incorporate 50 Ω termination
resistors, ESD protection, and a multizero transfer function
equalizer that can be optimized for backplane or cable operation.
Each channel also provides a programmable loss-of-signal (LOS)
function that provides an interrupt that can be used to squelch
or disable the associated output when the differential input voltage
falls below the programmed threshold value. Each receive channel
also provides a P/N inversion function that allows the user to
swap the sign of the input signal path to eliminate the need for
board-level crossovers in the receiver channel.
Table 5 illustrates some, but not all, possible combinations of
input supply voltages.
Table 5. Common Input Voltage Levels
Configuration
Low V
Single 1.8 V Supply
3.3 V Core
Single 3.3 V Supply
VCC
VTTI
VEE
IN
IP
TTI
, AC-Coupled Input
Figure 38. Simplified Input Structure
SIMPLIFIED RECEIVER INPUT CIRCUIT
52Ω
RP
RN
52Ω
750Ω
750Ω
R1
R2
R3
1kΩ
Q1
RLN
V
1.8
1.8
3.3
3.3
CC
(V)
Q2
I1
RLP
V
1.6
1.8
1.8
3.3
TTI
(V)