m48t129v STMicroelectronics, m48t129v Datasheet - Page 8

• Manufacturer Part Number: m48t129v
• Description: 5.0 Or 3.3v, 1 Mbit 128 Kbit X 8 Timekeeper Sram
• Manufacturer: STMicroelectronics

M48T129Y, M48T129V
READ Mode
The M48T129Y/V is in the READ Mode whenever
W (WRITE Enable) is high and E (Chip Enable) is
low. The unique address specified by the 17 Ad-
dress Inputs defines which one of the 131,072
bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within t
dress Access Time) after the last address input
signal is stable, providing the E and G access
times are also satisfied. If the E and G access
times are not met, valid data will be available after
Figure 6. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms
Figure 7. Address Controlled, READ Mode AC Waveforms
8/30
A0-A16
E
G
DQ0-DQ7
A0-A16
DQ0-DQ7
DATA VALID
tAXQX
tAVQV
tELQX
AVQV
tELQV
tGLQX
tAVQV
tGLQV
(Ad-
tAVAV
VALID
tAVAV
VALID
the latter of the Chip Enable Access Times (t
or Output Enable Access Time (t
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before t
indeterminate state until t
puts are changed while E and G remain active,
output data will remain valid for t
Data Hold Time) but will go indeterminate until the
next Address Access.
DATA OUT
AVQV
tAXQX
, the data lines will be driven to an
DATA VALID
tGHQZ
AVQV
. If the Address In-
GLQV
tEHQZ
AI01197
AI02324
AXQX
).
(Output
ELQV
)