m48t129v STMicroelectronics, m48t129v Datasheet - Page 10

• Manufacturer Part Number: m48t129v
• Description: 5.0 Or 3.3v, 1 Mbit 128 Kbit X 8 Timekeeper Sram
• Manufacturer: STMicroelectronics

M48T129Y, M48T129V
WRITE Mode
The M48T129Y/V is in the WRITE Mode whenever
W (WRITE Enable) and E (Chip Enable) are low
state after the address inputs are stable.
The start of a WRITE is referenced from the latter
occurring falling edge of W or E. A WRITE is termi-
nated by the earlier rising edge of W or E. The ad-
dresses must be held valid throughout the cycle. E
or W must return high for a minimum of t
Figure 8. WRITE Enable Controlled, WRITE AC Waveforms
Figure 9. Chip Enable Controlled, WRITE AC Waveforms
10/30
A0-A16
E
W
DQ0-DQ7
A0-A16
E
W
DQ0-DQ7
tAVEL
tAVEL
tAVWL
tAVWL
EHAX
tWLQZ
from
tAVWH
tWLWH
tAVAV
VALID
tAVAV
VALID
tELEH
Chip Enable or t
the initiation of another READ or WRITE cycle.
Data-in must be valid t
WRITE and remain valid for t
should be kept high during WRITE cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G a low on W will
disable the outputs t
tDVWH
tDVWH
DATA INPUT
DATA INPUT
tWHDX
WHAX
WLQZ
tWHDX
from WRITE Enable prior to
DVWH
tWHQX
after W falls.
tEHAX
tWHAX
prior to the end of
WHDX
AI02382
AI02582
afterward. G