m41t81s STMicroelectronics, m41t81s Datasheet - Page 21

• Manufacturer Part Number: m41t81s
• Description: Serial Access Real-time Clock With Alarms
• Manufacturer: STMicroelectronics

Oscillator fail interrupt enable
Output driver pin
Note:
Preferred initial power-on default
If the Oscillator Fail Interrupt Bit (OFIE) is set to a '1,' the IRQ pin will also be activated. The
IRQ output is cleared by resetting the OFIE or OF Bit to '0' (not be reading the Flags
Register).
When the FT Bit, AFE Bit, SQWE Bit, and Watchdog Register are not set, the
IRQ/FT/OUT/SQW pin becomes an output driver that reflects the contents of D7 of the
Calibration Register. In other words, when D7 (OUT Bit) and D6 (FT Bit) of address location
08h are a '0,' then the IRQ/FT/OUT/SQW pin will be driven low.
The IRQ/FT/OUT/SQW pin is an open drain which requires an external pull-up resistor.
Upon initial application of power to the device, the following register bits are set to a '0' state:
Watchdog Register; AFE; ABE; SQWE; OFIE; and FT. The following bits are set to a '1'
state: ST; OUT; OF; and HT (see
Table 5.
1. BMB0-BMB4, RB0, RB1
2. State of other control bits undefined
3. UC = Unchanged
Initial Power-up
Subsequent Power-
up (with battery
back-up)
Condition
(3)
Preferred default values
(2)
UC
ST
1
HT
1
1
Out
UC
Table 5 on page
1
FT
0
0
AFE SQWE ABE
UC
0
21).
UC
0
UC
0
WATCHDOG
Register
0
0
(1)
OF
UC
1
OFIE
UC
21/31
0