pca82c200t NXP Semiconductors, pca82c200t Datasheet - Page 34

• Manufacturer Part Number: pca82c200t
• Description: 8-bit Microcontroller With On-chip Can
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Notes to the description of the CR bits
1. The test mode is intended for factory testing and not for customer use.
2. A modification of the bits Reference Active and Sync is only possible with Reset Request = HIGH (present). It is
3. During an external reset (RST = HIGH) or when the Bus Status bit is set HIGH (Bus-OFF), the IML forces the
1996 Jun 27
8-bit microcontroller with on-chip CAN
allowed to set these bits while Reset Request is changed from a HIGH level to a LOW level. After an external reset
(pin RST = HIGH) the Reference Active bit is set HIGH (output), the Sync bit is undefined.
Reset Request HIGH (present). After the Reset Request bit is set LOW (absent) the CAN-controller will wait for:
a) One occurrence of the Bus-Free signal (11 recessive bits, see Section 13.6.9.6), if the preceding reset (Reset
b) 128 occurrences of Bus-Free, if the preceding reset (Reset Request = HIGH) has been caused by a
c) When Reset Request is set HIGH (present), for whatever reason, the Control, Command, Status and Interrupt
BIT
5
4
3
2
1
0
Request = HIGH) has been caused by an external reset or a CPU initiated reset.
CAN-controller initiated Bus-OFF, before re-entering the Bus-On mode, see Section 13.6.9.
bits are affected, see Table 40. The registers at addresses 4 to 8 are only accessible when the Reset Request is
set HIGH (present).
RA
OIE
EIE
TIE
RIE
RR
SYMBOL
Reference Active (note 2). If the value of RA is:
Overrun Interrupt Enable. If the value of OIE is:
Error Interrupt Enable. If the value of EIE is:
Transmit Interrupt Enable. If the value of TIE is:
Receive Interrupt Enable. If the value of RIE is:
Reset Request (note 3). If the value of RR is:
HIGH (output), then the pin REF is an
LOW (input), then a reference voltage may be input.
HIGH (enabled) and the Data Overrun bit is set (see Section 13.5.5) then the CPU
receives an Overrun Interrupt signal.
LOW (disabled), then the CPU receives no Overrun Interrupt signal from the
CAN-controller.
HIGH (enabled) and the Error or Bus Status change (see Section 13.5.5) then the CPU
receives an Error Interrupt signal.
LOW (disabled), then the CPU receives no Error Interrupt signal.
HIGH (enabled) and when a message has been successfully transmitted or the
Transmit Buffer is accessible again, (e.g. after an Abort Transmission command), then
the CAN-controller transmits a Transmit Interrupt signal to the CPU.
LOW (disabled), then there is no transmission of the Transmit Interrupt signal by the
CAN-controller to the CPU.
HIGH (enabled) and when a message has been received without errors, then the
CAN-controller transmits a Receive Interrupt signal to the CPU.
LOW (disabled), then there is no transmission of the Receive Interrupt signal by the
CAN-controller to the CPU.
HIGH (present), then detection of a Reset Request results in the CAN-controller
aborting the current transmission/reception of a message entering the reset state
synchronously to the system clock (t
LOW (absent), on the HIGH-to-LOW transition of the Reset Request bit, the
CAN-controller returns to its normal operating state.
34
FUNCTION
SCL
1
2
, see Section 13.5.9).
AV
DD
reference output.
Product specification
P8xCE598