pcf85162 NXP Semiconductors, pcf85162 Datasheet - Page 21

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pcf85162

Manufacturer Part Number
pcf85162
Description
Universal Lcd Driver For Low Multiplex Rates
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
PCF85162_1
Product data sheet
The I
condition (S) from the I
slave addresses available. All PCF85162 whose SA0 inputs correspond to bit 0 of the
slave address respond by asserting an acknowledge in parallel. This I
ignored by all PCF85162 whose SA0 inputs are set to the alternative level.
After an acknowledgement, one or more command bytes follow, that define the status of
each addressed PCF85162.
The last command byte sent is identified by the continuation bit C set logic 0 (see
Figure
the bus.
After the last command byte, one or more display data bytes may follow. Display data
bytes are stored in the display RAM at the address specified by the data pointer and the
subaddress counter. Both data pointer and subaddress counter are automatically updated
and the data directed to the intended PCF85162 device.
An acknowledgement after each byte is asserted only by the PCF85162 that are
addressed via address lines A0, A1, and A2. After the last display byte, the I
master asserts a STOP condition (P). Alternately a START may be asserted to restart an
I
2
Fig 15. I
Fig 16. Format of command byte
C-bus access.
2
C-bus protocol is shown in
16). The command bytes are also acknowledged by all addressed PCF85162 on
2
S
C-bus protocol
0 1 1 1 0 0
slave address
1 byte
Rev. 01 — 7 January 2010
2
C-bus master which is followed by one of two possible PCF85162
S
A
0
R/W
MSB
0 A C
C
Figure
acknowledge by
all addressed
n
PCF85162
≥ 1 byte(s)
COMMAND
REST OF OPCODE
15. The sequence is initiated with a START
Universal LCD driver for low multiplex rates
A
msa833
DISPLAY DATA
n
LSB
≥ 0 byte(s)
by A0, A1 and A2
update data pointers
subaddress counter
PCF85162 only
and if necessary,
acknowledge
PCF85162
selected
2
C-bus transfer is
© NXP B.V. 2010. All rights reserved.
A
013aaa235
P
2
C-bus
21 of 39

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