pcf85162 NXP Semiconductors, pcf85162 Datasheet - Page 18

• Manufacturer Part Number: pcf85162
• Description: Universal Lcd Driver For Low Multiplex Rates
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF85162_1
Product data sheet
7.16.1 Bit transfer
7.16.2 START and STOP conditions
7.16 Characteristics of the I
Table 6.
[1]
The entire display can blink at a frequency other than the nominal blink frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see
The I
The two lines are a Serial Data Line (SDA) and a Serial Clock Line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START
condition (S).
Blink mode
off
1
2
3
Fig 11. Bit transfer
The blink frequency is proportional to the oscillator frequency (f
see
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
Table
Blink frequencies
17.
Blink
frequency
equation
-
f
f
f
SDA
blink
SCL
blink
blink
=
=
=
Rev. 01 — 7 January 2010
--------- -
768
------------ -
1536
------------ -
3072
f
clk
f
f
clk
clk
[1]
2
C-bus
Blink frequency range
Min
f
blinking off
1.25
0.63
0.31
clk
data valid
data line
= 960 Hz
stable;
Figure
Universal LCD driver for low multiplex rates
allowed
change
of data
Typ
f
2.57
1.28
0.64
clk
Table
11).
= 1970 Hz
clk
10).
). For the range of the oscillator frequency
Max
f
3.44
1.72
0.86
clk
mba607
PCF85162
= 2640 Hz
© NXP B.V. 2010. All rights reserved.
18 of 39
Unit
-
Hz
Hz
Hz