mc145201dt Freescale Semiconductor, Inc, mc145201dt Datasheet - Page 16

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mc145201dt

Manufacturer Part Number
mc145201dt
Description
2.0 Ghz Pll Frequency Synthesizers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
CRYSTAL OSCILLATOR CONSIDERATIONS
erence frequency to Motorola’s CMOS frequency synthe-
sizers.
Use of a Hybrid Crystal Oscillator
oscillators (TCXOs) or crystal–controlled data clock oscilla-
tors provide very stable reference frequencies. An oscillator
capable of CMOS logic levels at the output may be direct or
dc coupled to REF in . If the oscillator does not have CMOS
logic levels on the outputs, capacitive or ac coupling to REF in
may be used (see Figure 8).
oscillators, please consult the latest version of the eem Elec-
tronic Engineers Master Catalog, the Gold Book, or similar
publications.
Design an Off–Chip Reference
discrete transistors or ICs specifically developed for crystal
oscillator applications, such as the MC12061 MECL device.
The reference signal from the MECL device is ac coupled to
REF in (see Figure 8). For large amplitude signals (standard
CMOS logic levels), dc coupling may be used.
Use of the On–Chip Oscillator Circuitry
propriate crystal may be used to provide a reference source
MC145200 MC145201
16
The following options may be considered to provide a ref-
Commercially available temperature–compensated crystal
For additional information about TCXOs and data clock
The user may design an off–chip crystal oscillator using
The on–chip amplifier (a digital inverter) along with an ap-
V H = High voltage level
V L = Low voltage level
*At this point, when both f R and f V are in phase, the output source and sink circuits are turned on for a short interval.
NOTE: The PD out either sources or sinks current during out–of–lock conditions. When locked in phase and frequency, the
f in (N 64 + A)
REFERENCE
FEEDBACK
REF in R
output is high impedance and the voltage at that pin is determined by the low–pass filter capacitor. PD out , R , and
V are shown with the polarity bit (POL) = low; see Figure 14 for POL.
PD out
DESIGN CONSIDERATIONS
LD
f R
f V
R
V
Figure 18. Phase/Frequency Detectors and Lock Detector Output Waveforms
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure 19.
(C L ) which does not exceed approximately 20 pF when used
at the highest operating frequency of 15 MHz. Assuming
R1 = 0 , the shunt load capacitance (C L ) presented across
the crystal can be estimated to be:
where
C1 and C2 = external capacitors (see Figure 19)
portion or all of C1 variable. The crystal and associated com-
ponents must be located as close as possible to the REF in
and REF out pins to minimize distortion, stray capacitance,
stray inductance, and startup stabilization time. Circuit stray
capacitance can also be handled by adding the appropriate
stray value to the values for C in and C out . For this approach,
the term C stray becomes 0 in the above expression for C L .
The crystal should be specified for a loading capacitance
The oscillator can be “trimmed” on–frequency by making a
C stray = the total equivalent external circuit stray
C out = 6 pF (see Figure 20)
C a = 1 pF (see Figure 20)
C in = 5 pF (see Figure 20)
C L =
capacitance appearing across the crystal
terminals
C in +C out
C in C out
*
+ C a + C stray +
V L
V L
V L
V L
V L
V H
V H
V H
V H
V H
SOURCING CURRENT
FLOAT
SINKING CURRENT
C1 + C2
C1 C2
MOTOROLA

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