mc145201dt Freescale Semiconductor, Inc, mc145201dt Datasheet - Page 11

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mc145201dt

Manufacturer Part Number
mc145201dt
Description
2.0 Ghz Pll Frequency Synthesizers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
V PD
Positive Power Supply (Pin 5)
A and B. The voltage applied on this pin must be no less than
the potential applied to the V DD pin. The maximum voltage
can be + 9.5 V with respect to the GND pin for the MC145200
and + 5.5 V for the MC145201.
MOTOROLA
Table 2. PD out Current, C1 = Low with OUTPUT A NOT
This pin supplies power to both phase/frequency detectors
ENB
CLK
NOTE: It may not be convenient to control the ENB or CLK pins during power up per the Pin Descriptions. If this is the case, the part may
NOTE: For information on spurious current measurement see AN1253/D, “An Improved PLL Design Method Without n and ”.
D in
Nominal PD out Spurious Current vs f R Frequency
Selected as “Port”; Also, Default Mode When
be initialized through the serial port as shown in the figure above. The sequence is similar to accessing the registers except that the
CLK must remain high at least 100 ns after ENB is brought high. Note that 3 groups of 5 bits are needed.
1
C3
0
0
1
1
(kHz)
OUTPUT A Selected as “Port”
100
200
f R
10
20
50
(1 V
2
t
PD out
MC145200
3
C2
0
1
0
1
t
4
V PD – 1V)
Figure 13. Initializing the PLL through the Serial Port
PD out Current
(RMS nA)
Current
5
320
1.6
5.3
22
95
100%
70%
80%
90%
100 ns MINIMUM
1
2
3
GND using a low–inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.
GND
Ground (Pin 7)
Table 3. PD out Current, C1 = High with OUTPUT A NOT
For optimum performance, V PD should be bypassed to
Common ground.
Nominal PD out Spurious Current vs f R Frequency
4
5
C3
0
0
1
1
(kHz)
100
200
f R
10
20
50
(1 V
Selected as “Port”
t
1
PD out
MC145201
C2
0
1
0
1
2
t
V PD – 1V)
MC145200 MC145201
3
PD out Current
(RMS nA)
Current
4
244
3.6
4.6
17
75
100%
25%
50%
75%
5
11

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