mc145201dt Freescale Semiconductor, Inc, mc145201dt Datasheet - Page 13

• Manufacturer Part Number: mc145201dt
• Description: 2.0 Ghz Pll Frequency Synthesizers
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
C3, C2 — I2, I1:
C6 — PDA/B:
C0 — Out B:
C4 — STBY:
C7 — POL:
C5 — LDE:
C1 — Port:
* At this point, the new byte is transferred to the C register and stored. No other registers are
affected.
ized. Immediately after the jam load, the A, N, and R counters begin counting down together. At
this point, the f R and f V pulses are enabled to the phase and lock detectors. (Patented feature.)
Selects the output polarity of the phase/frequency detectors. When set high, this bit inverts the polarity
of PD out and interchanges the R function with V as depicted in Figure 18. Also see the phase detector
output pin descriptions for more information. This bit is cleared low at power up.
Selects which phase/frequency detector is to be used. When set high, enables the output of phase/
frequency detector A (PD out ) and disables phase/frequency detector B by forcing R and V to the
static high state. When cleared low, phase/frequency detector B is enabled ( R and V ) and phase/fre-
quency detector A is disabled with PD out forced to the high–impedance state. This bit is cleared
low at power up.
Enables the lock detector output (LD) when set high. When the bit is cleared low, the LD output
is forced to a static low level. This bit is cleared low at power up.
When set high, places the CMOS section of device, which is powered by the V DD and V PD pins,
in the standby mode for reduced power consumption: PD out is forced to the high–impedance state,
is shut off. In standby, the state of LD is determined by bit C5. C5 low forces LD low (no change).
C5 high forces LD static high. During standby, data is retained in the A, R, and C registers. The
condition of REF/OSC circuitry is determined by the control bits in the R register: R13, R14, and
R15. However, if REF out = static low is selected, the internal feedback resistor is disconnected and
the input is inhibited when in standby; in addition, the REF in input only presents a capacitive load.
NOTE: Standby does not affect the other modes of the REF/OSC circuitry.
When C4 is reset low, the part is taken out of standby in 2 steps. First, the REF in (only in one mode)
resistor is reconnected, all counters are enabled, and the Rx current is enabled. Any f R and f V signals
are inhibited from toggling the phase/frequency detectors and lock detector. Second, when the first
f V pulse occurs, the R counter is jam loaded, and the phase/frequency and lock detectors are initial-
Controls the PD out source/sink current per Tables 2 and 3. With both bits high, the maximum current
(as set by Rx per Figure 14) is available. Also, see C1 bit description.
When the OUTPUT A pin is selected as “Port” via bits A22 and A23, C1 determines the state of
OUTPUT A. When C1 is set high, OUTPUT A is forced high; C1 low forces OUTPUT A low. When
OUTPUT A is NOT selected as “Port,” C1 controls whether the PD out step size is 10% or 25%. (See
Tables 2 and 3.) When low, steps are 10%. When high, steps are 25%. Default is 10% steps when
OUTPUT A is selected as “Port.” The Port bit is not affected by the standby mode.
Determines the state of OUTPUT B. When C0 is set high, OUTPUT B is high–impedance; C0 low
forces OUTPUT B low. The Out B bit is not affected by the standby mode. This bit is cleared low
at power up.
ENB
CLK
R and V are forced high, the A, N, and R counters are inhibited from counting, and the Rx current
D in
Figure 15. C Register Access and Format (8 Clock Cycles are Used)
MSB
C7
1
C6
2
C5
3
C4
4
C3
5
C2
6
C1
7
LSB
C0
8
*
MC145200 MC145201
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