mk2069-02 Integrated Device Technology, mk2069-02 Datasheet - Page 6

• Manufacturer Part Number: mk2069-02
• Description: Vcxo-based Clock Jitter Attenuator And Translator
• Manufacturer: Integrated Device Technology

Setting the VCXO PLL Loop Response.
The VCXO PLL loop response is determined both by fixed
device characteristics and by other characteristics set by the
user. This includes the values of R
shown in the External VCXO PLL Components figure on this
page.
The VCXO PLL loop bandwidth is approximated by:
The above equation calculates the “normalized” loop
bandwidth (denoted as “NBW”) which is approximately
equal to the - 3dB bandwidth. NBW does not take into
account the effects of damping factor or the second pole
imposed by C
approximation of filter performance.
To prevent jitter on VCLK due to modulation of the VCXO
PLL by the phase detector frequency, the following general
rule should be observed:
.
IDT® VCXO-BASED CLOCK JITTER ATTENUATOR AND TRANSLATOR
MK2069-02
VCXO-BASED CLOCK JITTER ATTENUATOR AND TRANSLATOR
NBW(VCXO PLL)
DF(VCLK)
The PLL loop damping factor is determined by:
NBW(VCXO PLL)
Where:
R
I
K
PV = PV Divider value = 2 to 4097
FV = FV Divider value= 1 to 4096
SV = SV Divider value= 1,2,4,6,8,10,12 or 16
Where:
CP
O
S
= Value of resistor R
= VCXO Gain in Hz/V
= Charge pump current in amps
(see table on page 8)
(see table on page 8)
P
. It does, however, provide a useful
=
R
----- -
2
S
=
f(Phase Detector)
-------------------------------------- -
-------------------------------------
PV
I
--------------------------------------------------
2
CP
R
S
PV
FV
C
S
20
S
I
in loop filter in Ohms
CP
S
, C
K
SV
FV
O
S
K
, C
O
SV
P
and R
SET
as
6
The above equations illustrate that the VCXO PLL
bandwidth and damping factor, together, can be increased
or decreased by changing only the value of the PV Divider.
The frequency multiplication ratio is not changed. This is a
feature unique to the MK2069-02.
External VCXO PLL Components
In general, the loop damping factor should be 0.7 or greater
to ensure output stability. A higher damping factor will create
less peaking in the passband and will further assure output
stability with the presence of system and power supply
noise. A damping factor of 4 will ensure a passband peak
less then 0.2dB which may be required for network clock
wander transfer compliance. A higher damping factor may
Crystal Tuning
C
DON'T STUFF
Refer to "Crystal Tuning Load
Capacitors" Section
Capacitors
C
P
Optional
S
= Value of capacitor C
C
C
L
L
C
R
R
S
S
XTAL
SET
ISET
LFR
X1
X2
LF
VCXO AND SYNTHESIZER
S
1
2
3
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MK2069-02
in loop filter in Farads
REV G 050203
56
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