mk2069-02 Integrated Device Technology, mk2069-02 Datasheet

no-image

mk2069-02

Manufacturer Part Number
mk2069-02
Description
Vcxo-based Clock Jitter Attenuator And Translator
Manufacturer
Integrated Device Technology
Datasheet
VCXO-BASED CLOCK JITTER ATTENUATOR AND TRANSLATOR
Description
The MK2069-02 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock generator that offers system
synchronization, jitter attenuation and frequency
translation. It can accept an input clock over a wide range of
frequencies and produces a de-jittered, low phase noise
clock output. The device is optimized for user configuration
by providing access to all major PLL divider functions. No
power-up programming is needed as configuration is pin
selected. External VCXO loop filter components provide an
additional level of performance tailoring.
The MK2069-02 features an adjustable phase detector
frequency, independent of the PLL frequency multiplication
factor, providing digital control over jitter attenuation
characteristics. This is accomplished by two internal,
programmable parallel dividers just prior to the phase
detector. One divider is applied to the reference input clock,
the other is applied to the PLL feedback clock. Adjustment
of the phase detector frequency influences PLL loop
bandwidth, damping factor, input clock jitter frequency
aliasing and input jitter tolerance.
Block Diagram
IDT® VCXO-BASED CLOCK JITTER ATTENUATOR AND TRANSLATOR
IC L K
C L R
P V 1 1 :0
V C X O
P L L
12
P V D iv id e r
P V D iv id e r
2 to 4 0 9 7
2 to 4 0 9 7
IS E T
D etector
P hase
L F
L F R
C harge
P um p
F V D iv id e r
X 1
P u llab le
F V 1 1 :0
1 -4 0 9 6
V C X O
xta l
12
X 2
1 ,2 ,4 ,6 ,8 ,
1 0 ,1 2 ,1 6
D iv id er
S V 2 :0
S V
1
L o c k D e te c to r
3
Features
L D C
Phase detector frequency is selectable over a wide range
with integer resolution. This allows control over various
PLL parameters such as loop bandwidth and jitter
attenuation characteristics.
Input clock frequency of <2kHz to 27MHz
Output clock frequency of 500kHz to 160MHz
PLL lock status output
VCXO-based clock generation offers very low jitter and
phase noise generation, even with low frequency or jittery
input clock.
PLL Clear function (CLR input) allows the VCXO to
free-run, offering a short term holdover function.
2nd PLL provides frequency translation of VCXO PLL to
higher or alternate output frequencies.
Device will free-run in the absence of an input clock (or
stopped input clock) based on the VCXO frequency
pulled to minimum frequency limit.
Low power CMOS technology
56 pin TSSOP package
Single 3.3V power supply
T ran s la to r
P L L
L D R
F T D iv id e r
V C O
F T 2 :0
1 -8
3
D iv id e r
2 , 1 6
S T
S T
MK2069-02
DATASHEET
MK2069-02
G N D
V D D
4
4
REV G 050203
V C L K
O E V
T C L K
O E T
R C L K
O E R
L D
O E L

Related parts for mk2069-02

mk2069-02 Summary of contents

Page 1

... VCXO-BASED CLOCK JITTER ATTENUATOR AND TRANSLATOR Description The MK2069- VCXO (Voltage Controlled Crystal Oscillator) based clock generator that offers system synchronization, jitter attenuation and frequency translation. It can accept an input clock over a wide range of frequencies and produces a de-jittered, low phase noise clock output ...

Page 2

... For FV addresses 0-4094 Divide = Address + 2 : 4096 1 SV Divider Ratio FT0 FT Divider Ratio MK2069-02 REV G 050203 ...

Page 3

... Ground Digital ground connection. Power Lock detector threshold setting circuit connection. Refer to circuit on page 10. Output Reference Clock output, pre-divided phase detector feedback clock. Ground Ground connection for output drivers (VCLK, TCLK, RCLK, LD, LDR). 3 VCXO AND SYNTHESIZER Pin Description MK2069-02 REV G 050203 ...

Page 4

... SV1 56 SV2 Functional Description The MK2069- PLL (Phase Locked Loop) based clock generator that generates output clocks synchronized to an input reference clock. It contains two cascaded PLL’s with user selectable divider ratios. The first PLL is VCXO-based and uses an external pullable crystal as part of the normal “ ...

Page 5

... MK2069-02 VCXO-BASED CLOCK JITTER ATTENUATOR AND TRANSLATOR Application Information The MK2069- mixed analog / digital integrated circuit that is sensitive to PCB (printed circuit board) layout and external component selection. Used properly, the device will provide the same high performance expected from a canned VCXO-based hybrid timing device, but at a lower cost ...

Page 6

... PV Divider. The frequency multiplication ratio is not changed. This feature unique to the MK2069-02 External VCXO PLL Components in loop filter in Ohms In general, the loop damping factor should be 0.7 or greater to ensure output stability ...

Page 7

... Loop Filter Response Software P Online tools to calculate loop filter response can be found at www.idt.com/?app=calculators&source=support_menu. (external resistor) SET 1E ohms SET 7 VCXO AND SYNTHESIZER value that is too low use the filter P should be increased in value until it P 10E+6 Recommended Range of Operation MK2069-02 REV G 050203 is too P ...

Page 8

... Loop Filter Capacitor Type ) increases CP Loop filters must use specific types of capacitors. Recommendations for these capacitors can be found at www.idt.com/?app=calculators&source=support_menu. 8 VCXO AND SYNTHESIZER ) vs. XTAL Frequency MK2069-02 REV G 050203 ...

Page 9

... Hz 2.5 0.3dB at 3Hz 4 0.15dB at 5Hz 4.7 nF 140 Hz 5 0.15dB at 10Hz which minimizes cost and board space. S allowing a lower PV Divider setting for similar P , but an increased PV Divider setting to S MK2069-02 Notes 4,5 4 also must not be P REV G 050203 ...

Page 10

... This is not the case with the MK2069-02. Lock Detection The MK2069-02 includes a lock detection feature that indicates lock status of VCLK relative to the selected input reference clock. When phase lock is achieved (such as following power-up), the LD output goes high. When phase ...

Page 11

... VCXO-BASED CLOCK JITTER ATTENUATOR AND TRANSLATOR used, RLD can remain unstuffed and CLD can be replaced with a resistor (< 10 kohm). Power Supply Considerations As with any integrated clock device, the MK2069-02 has a special of set power supply requirements: • The feed from the system power supply must be filtered for noise that can cause output clock jitter ...

Page 12

... Other signal traces should be routed away from the MK2069-02. This includes signal traces on PCB traces just underneath the device layers adjacent to the ground plane layer used by the device. ...

Page 13

... In applications that especially sensitive to noise, such as SONET or G-Bit ethernet transceivers, some or all of the following crystal shielding techniques should be considered. This is especially important when the MK2069-02 is placed near high speed logic or signal traces. The following techniques are illustrated on the Recommended PCB Layout drawing. ...

Page 14

... If output LD is not used, RLD and CLD may be omitted. See text on page 11. 14 VCXO AND SYNTHESIZER CBD A CBB G 603 603 603 43 MK2069 603 40 39 RLD G 38 603 37 CLD G 36 603 MK2069-02 REV G 050203 ...

Page 15

... LDR pin. Use RCLK as the scope trigger. LDR will produce a negative pulse equal in length to the charge pump pulse. 3.5) Filter leakage can also be caused by the use of improper loop capacitors. Refer to the section titled ‘Loop Filter Capacitor Type’ on page 8. 15 VCXO AND SYNTHESIZER /20 MK2069-02 REV G 050203 ...

Page 16

... VCXO-BASED CLOCK JITTER ATTENUATOR AND TRANSLATOR Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK2069-02. These ratings, which are standard values for IDT industrial rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied ...

Page 17

... V XC max prior to the application of VDD, providing utility in hot-plug line card IH 17 VCXO AND SYNTHESIZER Min. Typ. Max. Units 3.15 3.3 3. VDD + V 0.4 -0.4 0.8 V 200 k VDD/2+1 VDD + V 0.4 VDD/2+1 5.5 V -0.4 VDD/2-1 V -10 +10 A -10 + VDD-0.4 V 2.4 V 0.4 V ±50 mA ± VDD V MK2069-02 REV G 050203 ...

Page 18

... Measured at VDD/ =15pF L t 0.8 to 2.0V, C =15pF VCXO AND SYNTHESIZER Min. Typ. Max. Units 13.5 27 MHz ±115 ±150 ppm -300 -150 ppm 0.002 27 MHz 10 nsec 0.001 27 MHz 0 105 2.5 160 MHz 0.5 VCLK Period 1 MK2069-02 REV G 050203 ...

Page 19

... Conditions t 2.0 to 0.8V, C =15pF 0.8 to 2.0V, C =15pF 2.0 to 0.8V, C =15pF Rising edges, C =15pF Rising edges, C =15pF Rising edges, C =15pF OUT 19 VCXO AND SYNTHESIZER Min. Typ. Max. Units 2 1.5 + MK2069-02 REV G 050203 ...

Page 20

... MK2069-02GI MK2069-02GITR MK2069-02GI While the information presented herein has been checked for both accuracy and reliability, IDT assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied ...

Page 21

... MK2069-02 VCXO-BASED CLOCK JITTER ATTENUATOR AND TRANSLATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc ...

Related keywords