pca2125 NXP Semiconductors, pca2125 Datasheet - Page 27

• Manufacturer Part Number: pca2125
• Description: Spi Real Time Clock / Calendar Semiconductors
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCA2125_00
Preliminary data sheet
6.11 3-line Serial Interface
Data transfer to and from the device is made via a 3 wire SPI interface. The data lines for
input and output are split to allow for alternative system wiring. The data input and output
line can be connected together to facilitate a bi-directional databus. The chip enable signal
is used to identify the transmitted data. Each data transfer is a byte, with the MSB sent
first (see
Table 39.
[1]
The transmission is controlled by the active high chip enable signal CE. The first byte
transmitted is the command byte. Subsequent bytes will be either data to be written or
data to be read. Date is captured on the rising edge of the clock and transferred internally
on the falling edge.
The command byte defines the address of the first register to be accessed and the
read/write mode. The address counter will auto increment after every access and will
reset to zero after the last valid register is accessed. The read/write bit (R/W) defines if the
following bytes will be read or write information.
Table 40:
In the following example, the seconds register is set to 45 seconds and the minutes
register to 10 minutes (see
Symbol
CE
SCL
SDI
SDO
Bit
7
6..4
3..0
Fig 18. Data transfer overview
Chip enable may not be wired permanently high.
Figure
Symbol
R/W
Sub Address, SA
Register Address, RA 00
Serial interface
Command byte definition
Function
chip enable input; active high
serial clock input
serial data input
serial data output
chip enable
data bus
18).
Rev. 00.11 — 30 January 2007
COMMAND
Figure
Value
0
1
001
HEX
19).
to 0F
DATA
[1]
HEX
Description
When inactive, the interface is reset. Pull-down
resistor included. Input may be higher than
V
When CE is inactive, input may float. Input may
be higher than V
When CE is inactive, input may float. Input may
be higher than V
the rising edge of SCL.
Push-pull output. Drives from V
Output data is changed on the falling edge of
SCL.
DD
Description
Data will be write data
Data will be read data
Other codes will cause the device to ignore
data transfer.
Valid address range.
.
DATA
SPI Real time clock / calendar
DD
DD
.
. Input data is sampled on
DATA
PCA2125
© NXP B.V. 2007. All rights reserved.
001aaf914
SS
to V
DD
.
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