sy89537l Micrel Semiconductor, sy89537l Datasheet - Page 4

• Manufacturer Part Number: sy89537l
• Description: Sy89537l 3.3v Precision Lvpecl And Lvds Programmable Multiple Output Bank Clock Synthesizer And Fanout Buffer
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
Pin Description
Power
Control and Configuration
December 2007
14, 27, 30, 36
Pin Number
Pin Number
11, 21, 22
2, 4
10
43
44
23
24
17
19
39
41
18
20
40
42
33
1
3
7
RSEL1, RSEL0
Exposed Pad
Pin Name
Pin Name
PSEL0
PSEL1
PSEL2
PSEL3
VCCO
GNDA
INSEL
VCCA
VCCD
SYNC
PEN0
PEN1
PEN2
PEN3
GND,
LSEL
LEN
LR
LF
Pin Function
Analog PLL Power Pin: Connects to “quiet” 3.3V supply. 3.3V power pins are not internally
connected on the die, and must be connected together on the PCB. Bypass with
0.1µF//0.01µF low ESR capacitors and place as close to the VCCA pin as possible.
Digital Logic Core Power Pin: VCCD connects to a 3.3V supply. Power pins are not internally
connected on the die, and must be connected together on the PCB. Bypass with
0.1µF//0.01µF low ESR capacitors and place bypass capacitors as close to the VCCD pin as
possible.
LVDS and LVPECL Output Driver Power Pins: The outputs can be powered from a 2.5V
supply or 3.3V supply. Connect all VCCO pins to the same power supply: 3.3V ±10% or 2.5V
±5%. Power pins are not internally connected on the die, and must be connected together on
the PCB. Bypass with 0.1µF//0.01µF low ESR capacitor and place as close to the VCCO pin
as possible.
PLL Ground: Connect to “quiet” ground. GNDA and GND are not internally connected on the
die, and must be connected on the PCB.
Ground: GND pins and exposed pad must both be connected to the most negative potential
of the chip ground.
Analog Input/Output: Provides the reference voltage for the PLL loop filter and is used with the
LF pin. See "External Loop Filter Considerations" for recommended loop filter values.
Analog Input/Output: Provides the loop filter node for the PLL. See “External Loop Filter
Considerations” for loop filter values.
TTL/CMOS Reference Input Pre-scaler. The two-bit input pre-scaler divides the input
reference frequency by /1, /2, /4, or /8. RSEL0 is the LSB bit. See "Reference Input Divider
Select Table," for proper decoding. The threshold voltage V
TTL/CMOS Input Select Control. Selects either XTAL or Reference (RFCK) input. Internal
25kΩ pull-up. The default is logic HIGH, and selects the XTAL input. The threshold voltage V
= V
Logic HIGH: XTAL Select
Logic LOW: Reference Input Select
TTL/CMOS input select control signal for the LVDS LOUT0-LOUT2 outputs. LSEL and LEN
are used to decode the selection and the post divider of the LVDS output bank. LSEL includes
an internal 25kΩ pull-up. See “LVDS Output and Frequency Select Table” for proper decoding.
The threshold voltage V
TTL/CMOS Input Enable Pin. Used to control the LOUT0-LOUT2 outputs and acts as a
frequency select pin. LEN and LSEL are used to decode the selection and the post divider of
the LVDS output bank. See the “LVDS Output and Frequency Select Table” for proper
decoding. LEN includes an internal 25kΩ pull-up. When disabled, LOUT0-LOUT2 outputs are
LOW, and the complimentary outputs are HIGH. The threshold voltage V
TTL/CMOS input select control signals for the PECL POUT0-POUT3 outputs. PSELx and
PENx are used together to decode the selection and post divider of the PECL outputs. PSELx
pins include an internal 25kΩ pull-up. The threshold voltage V
Frequency and Select Table" for proper decoding.
TTL/CMOS input enable pin. Used to control the POUT0-PECL2 outputs and acts as a
frequency select pins. PENx and PSELx are used together; see the “PECL Output and
Frequency Select Table” for proper decoding. PENx includes an internal 25kΩ pull-up. When
disabled, PECL0-PECL2 outputs are LOW. The threshold voltage V
TTL/CMOS output bank synchronization control. Internal 25kΩ pull-up. The default state is
HIGH. After any bank has been programmed, all PECL and LVDS outputs are synchronized
when the SYNC control pin is toggled with a HIGH-LOW-HIGH transition. See
“Synchronization” section for details. The threshold voltage V
Pin Function
CC
/2.
TH
= V
4
CC
/2.
[e-mail]
TH
TH
TH
= V
= V
= V
CC
CC
/2. Internal 25kΩ pull-up.
CC
TH
/2.
/2. See "PECL Output
= V
TH
CC
= V
/2.
M9999-121207-B
or [phone]
CC
/2.
SY89537L
TH