sy89537l Micrel Semiconductor, sy89537l Datasheet - Page 10

• Manufacturer Part Number: sy89537l
• Description: Sy89537l 3.3v Precision Lvpecl And Lvds Programmable Multiple Output Bank Clock Synthesizer And Fanout Buffer
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
Functional Description
Overall Function
The SY89537L integrated programmable clock
synthesizer and fanout buffer is part of a precision
PLL-based clock generation family optimized for
internal system clock generation for (FPGAs, ASICs,
NPU) applications.
Input MUX
The device’s input patent-pending MUX accepts both
a single-ended or differential reference clock; and a
14MHz to 18MHz series resonant crystal (XTAL). The
input MUX has built-in isolation, which minimizes
crosstalk between the two inputs. The input MUX
drives the PLLs phase detector, which expects a
frequency between 14MHz and 18MHz, therefore, the
reference clock can be a maximum frequency of
144MHz when the reference divider is set to: divide-
by-8. The minimum frequency that the reference
accepts is 14MHz when the reference divider is set at:
divide-by-1.
PLL VCO
The VCOs range of operation is from 2.352GHz to
3.024GHz, and the output frequency range is from
73.5MHz to 756MHz. The minimum output frequency
is calculated according to the following equation:
The maximum output frequency is calculated
according to the following equation:
Crystal Input and Oscillator Interface
The SY89537L features a fully integrated on-board
oscillator, which minimizes system implementation
cost. The oscillator is a series resonant, multi-vibrator
type crystal driver.
December 2007
f
f
f
f
f
OUT
OUT
OUT
OUT
OUT
(min)
(min)
(max)
(max)
=
PreDivider
fphase
=
=
=
=
14MHz
73.5MHz
756MHz
18MHz
×
2
2
Pre
×
×
×
2
×
2
OutoutDivi
×
×
Divider
2
×
2
8
×
1
×
84
84
×
FeedbackDi
der
×
PostDivide
vider
r
10
Oscillator Tips
Table 4 illustrates the crystal specifications. Figure 2
below illustrates how to interface the crystal with the
SY89537L.
Quartz Crystal Selection:
Note: Raltron Series Resonant: AS-16.666-S-SMD-T-MI (2) Raltron
External Loop Filter Considerations
The SY89537L features an external PLL loop filter
that allows the users to tailor the PLLs behavior. It is
recommended that ceramic capacitors with NPO or
X7R dielectric be used, since they have very low
effective series resistance. For applications that
require ultra-low, cycle-to-cycle jitter, use the
components shown in Figure 3a. For best total jitter
and best spur reduction, use the components shown
in Figure 3b. Larger values of the pole capacitor (C2)
results in less total jitter; however, the loop stability
decreases. Loop stability decreases since the pole
capacitor begins to dominate over the zero capacitor
(C1). The external loop filter allows the user to change
the loop filter values for specific jitter requirements.
Using a smaller resistor in the loop filter decreases the
PLLs loop bandwidth. This results in less noise from
the PLL input, but potentially more noise from the
VCO.
1. Mount the crystal as close to the SY89537L
2. Mount on the same plane as the SY89537 to
3. To minimize noise pick up on the loop filter
4. Keep the crystal and its traces away from
as possible to minimize parasitic effects.
minimize on via hole inductance.
pins, cut the ground plane directly underneath
the loop filter component pads and traces.
adjacent noisy traces to minimize on noise
coupling.
Figure 3a. Loop Filter for Lowest
Figure 2. Crystal Interface
Cycle-to-Cycle Jitter
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M9999-121207-B
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SY89537L