sy89537l Micrel Semiconductor, sy89537l Datasheet - Page 15

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sy89537l

Manufacturer Part Number
sy89537l
Description
Sy89537l 3.3v Precision Lvpecl And Lvds Programmable Multiple Output Bank Clock Synthesizer And Fanout Buffer
Manufacturer
Micrel Semiconductor
Datasheet

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Figure 6 shows the open and closed loop gain of the
SY89537L. The closed loop-gain plot shows that the
SY89537L when configured with the recommended
loop filter values has essentially no jitter peaking near
the -3dB point. In addition, the open loop curve shows
the frequency at which unity gain occurs for a typical
case of the SY89537L with V
At unity gain, Figure 7 can be used to determine the
phase margin or stability of the SY89537L.
Figure 8 illustrates the VCO frequency versus the loop
filter control voltage at 3.3V, T
loop filter control voltage is -300mV to +300mV.
Figure 9 illustrates the VCO gain curve at V
T
the loop stability with other sets of loop filter
configurations are possible.
December 2007
A
= 25°C. With this set of information, determining
Figure 6. Open and Closed Loop Gain
Figure 7. Phase Margin Plot
at V
at V
CC
CC
= 3.3V, T
= 3.3V, T
Frequency (Hz)
Frequency (Hz)
CC
A
A
A
= 25°C
= 25°C
= 3.3V at T
= 25°C. The normal
CC
A
= 25°C.
= 3.3V,
15
Input Interface
RFCK is designed to accept any differential or single-
ended input signal 300mV above V
GND. RFCK should not be left floating. Tie either the
true or complement input to GND, but not both. A logic
zero is achieved by connecting the complement input
to GND with the true input floating. For TTL input, tie a
2.5kΩ resistor between the complement input and
GND. LVDS, CML and HSTL differential signals may
be connected directly to the reference inputs.
Loop Filter Control Voltage at 3.3V, T
Loop Filter Control Voltage at 3.3V, T
Figure 10. Simplified Input Structure
Figure 8. VCO Frequency vs.
Figure 9. VCO Gain vs.
hbwhelp@micrel.com
CC
or 300mV below
M9999-121207-B
or (408) 955-1690
A
A
= 25°C
= 25°C
SY89537L

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