sy89537l Micrel Semiconductor, sy89537l Datasheet
sy89537l
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sy89537l Summary of contents
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... General Description The SY89537L integrated programmable clock synthesizer and fanout is part of a precision PLL- based clock generation family optimized for enterprise switch, router, and multiprocessor server applications. This family is ideal for generating internal system timing requirements up to 700MHz for multiple ASICs, FPGAs, and NPUs ...
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... Micrel, Inc. Functional Block Diagram December 2007 2 hbwhelp@micrel.com SY89537L M9999-121207-B or (408) 955-1690 ...
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... Tape and Reel. Pin Configuration December 2007 Operating Package Marking Range SY89537LMY Industrial with Pb-Free bar-line indicator SY89537LMY Industrial with Pb-Free bar-line indicator = 25°C, DC Electricals only. A ® 44-Pin MLF (MLF-44) 3 SY89537L Lead Finish Matte-Sn Pb-Free Matte-Sn Pb-Free M9999-121207-B hbwhelp@micrel.com or (408) 955-1690 ...
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... TTL/CMOS output bank synchronization control. Internal 25kΩ pull-up. The default state is HIGH. After any bank has been programmed, all PECL and LVDS outputs are synchronized when the SYNC control pin is toggled with a HIGH-LOW-HIGH transition. See “Synchronization” section for details. The threshold voltage V 4 SY89537L = V /2. Internal 25kΩ pull-up ...
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... Crystal Oscillator Specification” table. Place crystal as close to the input as possible, keep XTAL and traces away from adjacent noisy traces to minimize noise coupling, and place the XTAL on the same side as the SY89537L (component side). 100K LVPECL Output Drivers. Terminate all PECL outputs with 50Ω output pair has respective output frequency control (PSELx, PENx) pins. See " ...
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... CCD, CCA ) .............................+2.375V to +3.6V CCO ) .........................–40°C to +85°C A (3) (θ (ψ Min Typ Max 3.0 3.3 3.6 3.0 3.3 3.6 2.375 2.5 2.625 3.0 3.3 3.6 240 300 10 55 175 Min Typ Max 2.0 0.8 –125 150 –300 M9999-121207-B hbwhelp@micrel.com or (408) 955-1690 SY89537L Units Units V V µA µA and JA ...
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... CCO V –1.860 CCO See Figure 1a. 550 See Figure 1b. 1100 = 100Ω across the pair Condition Min See Figure 1a. 250 See Figure 1b. 500 1.125 7 SY89537L Typ Max Units V + 0.3 V CCD –2V –40°C to +85°C, unless A Typ Max Units V – ...
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... T where T is the time between rising edges of the n n-1 12 output edges will deviate by more hbwhelp@micrel.com SY89537L (LVPECL) L Max Units 18 MHz 144 MHz 18 MHz 756 MHz 3024 MHz 200 ...
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... Micrel, Inc. Single-Ended and Differential Swings Figure 1a. Single-Ended Voltage Swing December 2007 Figure 1b. Differential Voltage Swing 9 hbwhelp@micrel.com SY89537L M9999-121207-B or (408) 955-1690 ...
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... PLLs loop bandwidth. This results in less noise from the PLL input, but potentially more noise from the VCO Mount the crystal as close to the SY89537L as possible to minimize parasitic effects. 2. Mount on the same plane as the SY89537 to minimize on via hole inductance minimize noise pick up on the loop filter pins, cut the ground plane directly underneath the loop filter component pads and traces ...
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... Figure 5. ±5 ppm 50 _ µW 100 Note: For V CCA For V CCO 130Ω 0.47µ 1000pF) Figure 5. SY89537L Recommended Power Supply De-Coupling and V use ferrite bead, Murata P/N BLM21A1025. CCD use ferrite bead, Murata, P/N BLM31P005. M9999-121207-B hbwhelp@micrel.com or (408) 955-1690 SY89537L ...
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... SYNC Timing Diagram” for details. Once SYNC is December 2007 asserted with a rising edge, the outputs are enabled when all internal divider stages are reaching their LOW state. This ensures a simultaneous switching of all outputs with the next LOW-HIGH transition of the pre-divider clock. 12 hbwhelp@micrel.com SY89537L M9999-121207-B or (408) 955-1690 ...
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... M9999-121207-B hbwhelp@micrel.com or (408) 955-1690 SY89537L Units 3 3024 MHz A Ω 130 F F Hz/V 168 Integer 18 MHz 1.9 8668.52 Hz 624 ...
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... M9999-121207-B hbwhelp@micrel.com or (408) 955-1690 SY89537L Units 3 3024 MHz A Ω 130 F F Hz/V 168 Integer 18 MHz 1.9 8668.52 Hz 624 ...
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... Micrel, Inc. Figure 6 shows the open and closed loop gain of the SY89537L. The closed loop-gain plot shows that the SY89537L when configured with the recommended loop filter values has essentially no jitter peaking near the -3dB point. In addition, the open loop curve shows ...
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... Input Termination Figure 11a. LVPECL Interface (DC-Coupled) Figure 11d. CML Interface (AC-Coupled) Figure 11g. 2.5V CML (DC-Coupled) December 2007 Figure 11b. LVPECL Interface (AC-Coupled) Figure 11e. LVDS (DC-Coupled) 16 SY89537L Figure 11c. CML Interface (DC-Coupled) Figure 11f. 2.5V LVPECL (DC-Coupled) M9999-121207-B hbwhelp@micrel.com or (408) 955-1690 ...
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... LVDS driver and receiver. Also, change in common mode voltage function of data input, is kept to a minimum, to keep EMI low. Figure 13b. LVDS Common Mode Measurement 17 Figure 12a. Parallel Thevenin-Equivalent Figure 12b. Parallel Termination Figure 13a. LVDS Differential Measurement M9999-121207-B hbwhelp@micrel.com SY89537L or (408) 955-1690 ...
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... SY89538L 3.3V, Precision LVPECL and LVDS Programmable, Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay HBW Solutions New Products and Applications ® MLF Application Note December 2007 Data Sheet Link http://www.micrel.com/product-info/products/sy89538l.shtml www.micrel.com/product-info/products/solutions.shtml www.amkor.com/products/notes_papers/MLFAppNote.pdf 18 hbwhelp@micrel.com SY89537L M9999-121207-B or (408) 955-1690 ...
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... A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. December 2007 44-Pin MLF® (MLF-44) © 2005 Micrel, Incorporated. 19 SY89537L M9999-121207-B hbwhelp@micrel.com or (408) 955-1690 ...