ics9248-172 ETC-unknow, ics9248-172 Datasheet - Page 2

• Manufacturer Part Number: ics9248-172
• Description: Single Chip, System Clock Piii/1651 Chipset 147mhz; Sdram Clocks
• Manufacturer: ETC-unknow

Advance Information
Pin Descriptions
Notes:
1:
2:
3:
Third party brands and names are the property of their respective owners.
ICS9248-172
30, 31, 32, 33, 36,
37, 38, 39, 42, 43
3, 11, 16, 23, 29,
PIN N U MBER
6, 8, 17, 21, 28,
19, 15, 14, 13
34, 41, 48
to program logic Hi to VDD or GND for logic low.
Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
Internal Pull-down resistor of 120K to GND on indicated inputs.
46, 47
35, 40
1,45
10
12
18
20
22
24
25
27
28
44
2
4
5
7
9
SD RA M ( 9:0 )
CPU CLK (1:0)
CPU _STO P#
PCI_STO P#
PIN N A ME
PCICLK _F
SDRA M 12
SDRA M 11
SDRA M 10
(4, 2, 1, 0)
PCICLK 3
M O D E
PCICLK 5
PCICLK
IO APIC
SD A TA
48M H z
V D D L
FS0
FS1
FS2
FS3
A G P0
A G P1
SCLK
REF0
G N D
V D D
PD #
PD #
X 1
X 2
2, 3
2, 3
1, 3
2, 3
1
1
1, 3
1
1
TY PE
PWR
PWR
PWR
O U T
O U T
O U T
O U T
O U T
O U T
O U T
O U T
O U T
O U T
O U T
O U T
O U T
O U T
O U T
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Pow er supply pins, nominal 2.5V
2.5V clock outputs
Crystal input,nominally 14.318M H z.
Crystal output, nominally 14.318M H z.
Ground pins
Pow er supply pins, nominal 3.3V
Frequency select pin.
14.318 M Hz reference clock.
Frequency select pin.
AG P outputs defined as 2X PCI. These may not be stopped.
AG P outputs defined as 2X PCI. These may not be stopped.
Free running PCICLK not stoped by PCI_STO P#
Frequency select pin.
PCI clock outputs.
PCI clock output.
Function select pin, 1=D esktop M ode, 0=M obile M ode.
Asynchronous active low input pin used to power down the device into a low
pow er state. The internal clocks are disabled and the V CO and the crystal are
stopped. The latency of the power dow n w ill not be greater than 3ms. This pin
will be activiated w hen
PCI clock output.
Frequency select pin.
48M H z output clock
Clock input of I
Asynchronous active low input pin used to power down the device into a low
pow er state. The internal clocks are disabled and the V CO and the crystal are
stopped. The latency of the power dow n w ill not be greater than 3ms. This pin
will be activiated w hen
SD RA M clock output.
This asynchronous input halts CPU , SD RAM , and A G P clocks at logic "0"
level w hen driven low , the stop selection can be programmed through I
SD RA M clock output.
Stops all PCICLK sbesides the PCICLK _F clocks at logic 0 level,
when input low
SD RA M clock output.
SD RA M clock outputs.
Data input for I
2.5V CPU clocks
2
2
2
C serial input, 5V tolerant input
C input, 5V tolerant input
DESCR IPTION
2
C.