ics9248-127 ETC-unknow, ics9248-127 Datasheet
ics9248-127
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ics9248-127 Summary of contents
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... Systems, Inc. Frequency Generator & Integrated Buffers for PENTIUM/Pro General Description The ICS9248-127 is the single chip clock solution for Desktop designs using the VIA MVP4 and Aladdin 7 style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I Spread spectrum typically reduces system EMI by 8dB to 10dB ...
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... ICS9248-127 Pin Descriptions ...
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... ICS9248-127 ...
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... ICS9248-127 Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = ± ...
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... ICS9248-127 ...
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... ICS9248-127 Byte 4: Reserved Active/Inactive Register (1 = enable disable ...
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... V +/-5% (unless otherwise stated) CONDITIONS pF; Select @ 66M 3 Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From target Freq 1 ICS9248-127 +0 TYP MAX -0.3 0 180 14.318 5 27 ...
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... ICS9248-127 Electrical Characteristics - CPU 70C; VDD=3.3V +/-5 ETER SYM BOL 1 Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current ...
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... 0 0 2.4 V r2A 2 0.4 V f2A 1.5 V t2A 1.5 V sk2A 1.5 V sk2A T ICS9248-127 MIN TYP MAX UNITS 2.4 2.9 V 0.2 0.4 V -58 - 1.38 2.0 ns 1. 236 500 ps 214 ...
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... ICS9248-127 General I The information in this section assumes familiarity with I For more information, contact ICS for an I How to Write: How to Write: Controller (Host) ICS (Slave/Receiver) Start Bit Address D2 (H) Dummy Command Code Dummy Byte Count Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Stop Bit 1 ...
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... Shared Pin Operation - Input/Output Pins Programming Header Via to Gnd Device Pad Via to VDD 2K 8.2K Clock trace to load Series Term. Res. Fig. 1 ICS9248-127 ...
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... CLK_STOP asychronous input to the clock synthesizer used to turn off the CPU clocks for low power operation. CLK_STOP# is synchronized by the ICS9248-127. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse ...
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... PCI_STOP# Timing Diagram PCI_STOP asynchronous input to the ICS9248-127 used to turn off the PCICLK [4:0] clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-127 internally. The minimum that the PCICLK [4:0] clocks are enabled (PCI_STOP# high pulse least 10 PCICLK [4:0] clocks. PCICLK [4:0] clocks are stopped in a low state and started with a full high pulse width guaranteed ...
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... ICS9248-127 Ordering Information ICS9248yF-127-T Example: ICS XXXX PPP - T Designation for tape and reel packaging Pattern Number ( digit number for parts with ROM code patterns) Package Type Revision Designator (will not correlate with datasheet revision) Device Type (consists digit numbers) ...