ics9248-179 ETC-unknow, ics9248-179 Datasheet
ics9248-179
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ics9248-179 Summary of contents
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... Note: Please see full table on page 4. PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. ICS9248-179 Pin Configuration 1 48 VDDLAPIC 2 47 IOAPIC GND 4 45 ...
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... ICS9248-179 Preliminary Product Preview Pin Configuration PIN NUMBER PIN NAME 1, 11, 17, 21, VDD 25, 36 FS0 2 REF0 FS1 3 REF1 14, 20, 24, GND 26, 34, 39, 42 FS2 9 PCICLK_F FS3 10 PCICLK0 FS4 12 PCICLK1 16, 15, 13 PCICLK (4:2) 19, 18 AGPCLK (1:0) 22 48MHz AGPSEL 23 24_48M Hz 27 SCLK ...
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... General Description The ICS9248-179 is the single chip clock solution for Desktop/Notebook designs using the SIS 635/640 style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-179 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations ...
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... ICS9248-179 Preliminary Product Preview Serial Configuration Command Bitmap Bytes 0-3: Are reserved for external clock buffer. Byte4: Functionality and Frequency Select Register (default = ...
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... ICS9248-179 Preliminary Product Preview ...
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... ICS9248-179 Preliminary Product Preview Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0 Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied ...
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... ICS9248-179 Preliminary Product Preview MIN TYP MAX 1 1.2 0.4 18 0.9 0.9 V pullup(external) 0.4 + 0.6 V pullup(external) 0.2 + 0.6 550 1100 45 55 200 250 -250 +250 is the "true" TR /2)+150mV ...
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... ICS9248-179 Preliminary Product Preview Electrical Characteristics - PCI 70C 3.3 V +/-5 PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Window Jitter 1 Guarenteed by design, not 100% tested in production. ...
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... Index Block Read Operation Controller (Host) T Slave Address D2 WR ACK Beginning Byte = N ACK RT ACK Slave Address D3 RD ACK ACK ICS9248-179 . ICS (Slave/Receiver) starT bit (H) WRite ACK ACK Repeat starT (H) ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK Byte ...
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... ICS9248-179 Preliminary Product Preview Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS9248- 179 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch ...
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... CPU_STOP asychronous input to the clock synthesizer used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9248-179. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse ...
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... Preliminary Product Preview PCI_STOP# Timing Diagram PCI_STOP asynchronous input to the ICS9248-179 used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-179 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed ...
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... SDRAM_STOP asychronous input to the clock synthesizer used to stop SDRAM clocks for low power operation. SDRAM_STOP# is synchronized to complete it's current cycle, by the ICS9248-179. All other clocks will continue to run while the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse ...
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... Crystal Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-179 device shown, the outputs Stop Low on the next falling edge after PD# goes low asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. ...
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... Device Type (consists digit numbers) Prefix ICS Standard Device PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. 15 Characteristic data and other specifications are subject to change without notice. ICS9248-179 In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN 2 ...