ics9248-151 ETC-unknow, ics9248-151 Datasheet - Page 11

• Manufacturer Part Number: ics9248-151
• Description: Single Chip Clock Apollo With 200mhz Frequency Support
• Manufacturer: ETC-unknow

Notes:
1. All timing is referenced to the internal CPU clock.
2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is
3. IOAPIC output is Stopped Glitch Free by CLK_STOP# going low.
4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-151
5. All other clocks continue to run undisturbed.
0353D—08/03/04
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power
operation. CLK_STOP# is synchronized by the ICS9248-151. The minimum that the CPU clock is enabled (CLK_STOP#
high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks
will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
synchronized to the CPU clocks inside the ICS9248-151.
CLK_STOP# signal. SDRAM's are controlled as shown.
PCI_STOP# (High)
CLK_STOP#
INTERNAL
CPUCLK
PCICLK
IOAPIC
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ICS9248-151