ics9248-134 ETC-unknow, ics9248-134 Datasheet - Page 11

• Manufacturer Part Number: ics9248-134
• Description: Frequency Timing Generator Pentium Ii/iii Systems
• Manufacturer: ETC-unknow

How to Write:
1.
2.
3.
4.
5.
6.
The ICS clock generator is a slave/receiver, I
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
Dummy Command Code
Dummy Byte Count
Controller (Host)
Address
Start Bit
Stop Bit
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
D2
(H)
How to Write:
For more information, contact ICS for an I
The information in this section assumes familiarity with I
ICS (Slave/Receiver)
General I
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
2
C serial interface information
2
C component. It can read back the data stored in the latches for
2
C programming application note.
How to Read:
Controller (Host)
Address
Start Bit
Stop Bit
2
D3
ACK
ACK
ACK
ACK
ACK
ACK
ACK
C programming.
(H)
How to Read:
ICS (Slave/Receiver)
ICS9248-134
Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK