ics8745b-21 Integrated Device Technology, ics8745b-21 Datasheet - Page 13

• Manufacturer Part Number: ics8745b-21
• Description: 1 1 Differential-to-lvds Zero Delay Clock Generator
• Manufacturer: Integrated Device Technology

Schematic Example
The schematic of the ICS8745B-21 layout example is shown in
Figure 5A. The ICS8745B-21 recommended PCB board layout for
this example is shown in Figure 5B. This layout example is used as
Figure 5A. ICS8745B-21 LVDS Zero Delay Buffer Schematic Example
IDT™ / ICS™ LVDS ZERO DELAY CLOCK GENERATOR
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
SP = Space (i.e. not intstalled)
RU3
1K
RD3
SP
VDD
RU4
1K
RD4
SP
3.3V
3.3V PECL Driver
RU5
SP
RD5
1K
RU6
1K
RD6
SP
Zo = 50 Ohm
Zo = 50 Ohm
(155.52 MHz)
SEL3
RU7
SP
PLL_SEL
SEL0
SEL1
SEL2
RD7
1K
R8
50
R10
50
R9
50
Bypass capacitors located
near the power pins
(U1-7)
R2
100
SEL2
0.1uF
C4
VDDO
VDDO
ICS8745B-21
(U1-11)
10
1
2
3
4
5
6
7
8
9
U1
CLK
nCLK
MR
nFB_IN
FB_IN
SEL2
VDDO
nQFB
QFB
GND
0.1uF
C2
13
a general guideline. The layout in the actual system will depend on
the selected component types, the density of the components, the
density of the traces, and the stack up of the P.C. board.
PLL_SEL
VDD=3.3V
VDDO=3.3V
SEL[3:0] = 0101,
Divide by 2
VDDO
VDDA
VDDI
SEL1
SEL0
SEL3
GND
nQ
Q
20
19
18
17
16
15
14
13
12
11
PLL_SEL
SEL3
VDDA
SEL1
SEL0
VDD
VDDO
Zo = 100 Ohm Differential
ICS8745BM-21REV. C OCTOBER 27, 2008
C1
0.1uF
0.01u
C11
(77.76 MHz)
10u
C16
10
R7
R4
100
VDD
+
-
LVDS_input