ics8430ay62l Integrated Device Technology, ics8430ay62l Datasheet - Page 4

• Manufacturer Part Number: ics8430ay62l
• Description: Ics8430-62 500mhz, Crystal-to-3.3v, 2.5v Differential Lvpecl Frequency Synthesizer
• Manufacturer: Integrated Device Technology

ICS8430-62 Datasheet
Function Tables
Table 3A. Parallel and Serial Mode Function Table
NOTE: L = LOW
Table 3B. Programmable VCO Frequency Function Table
NOTE 1: These M divide values and the resulting frequencies correspond to a REF_CLK or crystal frequency of 16MHz.
ICS8430AY-62 REVISION A JULY 2, 2009
MR
VCO Frequency
H
L
L
L
L
L
L
L
(MHz)
250
251
252
253
498
499
500
H = HIGH
X = Don’t care
↑ = Rising edge transition
↓ = Falling edge transition
nP_LOAD
•
•
X
H
H
H
H
H
L
↑
Data
Data
M
X
X
X
X
X
X
M Divide
250
251
252
253
498
499
500
•
•
Data
Data
N
X
X
X
X
X
X
Inputs
S_LOAD
256
M8
H
0
0
0
0
1
1
1
X
X
↑
↓
•
•
L
L
L
S_CLOCK
128
M7
1
1
1
1
1
1
1
•
•
X
X
X
↑
X
↑
L
L
M6
64
1
1
1
1
1
1
1
•
•
S_DATA
Data
Data
Data
Data
4
X
X
X
X
500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
M5
32
1
1
1
1
1
1
1
•
•
Conditions
Reset. Forces true outputs LOW.
Data on M and N inputs passed directly to the M divider
and N output divider. TEST output forced LOW.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
M4
16
1
1
1
1
1
1
1
•
•
M3
8
1
1
1
1
0
0
0
•
•
M2
4
0
0
1
1
0
0
1
•
•
©2009 Integrated Device Technology, Inc.
M1
2
1
1
0
0
1
1
0
•
•
M0
1
0
1
0
1
0
1
0
•
•